From 4621abca89bed9b22b27c4934268a62f7f7ff52e Mon Sep 17 00:00:00 2001 From: hartytp Date: Wed, 19 Sep 2018 15:42:56 +0100 Subject: [PATCH] sayma rtm: add clock mezzanine GPIO (#133) --- migen/build/platforms/sinara/sayma_rtm.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/migen/build/platforms/sinara/sayma_rtm.py b/migen/build/platforms/sinara/sayma_rtm.py index fe02ae57c..dd92de92b 100644 --- a/migen/build/platforms/sinara/sayma_rtm.py +++ b/migen/build/platforms/sinara/sayma_rtm.py @@ -123,6 +123,13 @@ Subsignal("rst_n", Pins("J5")), IOStandard("LVCMOS33") ), + + ("clk_mez", 0, + Subsignal("gpio", Pins("D18 C17 C18 G17" + "F18 H16 G15 G15" + "F15 G14 F14 H17" + "H18 F17 H14 E18")), + IOStandard("LVCMOS33")), ]