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New 'specials' API

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1 parent e82ea19 commit 49cfba50fabfed542980e7dca4683bef2fbb4110 @sbourdeauducq sbourdeauducq committed Feb 22, 2013
@@ -1,50 +1,60 @@
from migen.fhdl.structure import *
+from migen.fhdl.specials import Instance
+from migen.bus import wishbone
from migen.fhdl import verilog
class LM32:
def __init__(self):
- self.inst = Instance("lm32_top",
+ self.ibus = i = wishbone.Interface()
+ self.dbus = d = wishbone.Interface()
+ self.interrupt = Signal(32)
+ self.ext_break = Signal()
+ self._i_adr_o = Signal(32)
+ self._d_adr_o = Signal(32)
+ self._inst = Instance("lm32_top",
Instance.ClockPort("clk_i"),
Instance.ResetPort("rst_i"),
-
- Instance.Input("interrupt", 32),
- Instance.Input("ext_break", 1),
-
- Instance.Output("I_ADR_O", 32),
- Instance.Output("I_DAT_O", 32),
- Instance.Output("I_SEL_O", 4),
- Instance.Output("I_CYC_O", 1),
- Instance.Output("I_STB_O", 1),
- Instance.Output("I_WE_O", 1),
- Instance.Output("I_CTI_O", 3),
- Instance.Output("I_LOCK_O", 1),
- Instance.Output("I_BTE_O", 1),
- Instance.Input("I_DAT_I", 32),
- Instance.Input("I_ACK_I", 1),
- Instance.Input("I_ERR_I", 1),
- Instance.Input("I_RTY_I", 1),
- Instance.Output("D_ADR_O", 32),
- Instance.Output("D_DAT_O", 32),
- Instance.Output("D_SEL_O", 4),
- Instance.Output("D_CYC_O", 1),
- Instance.Output("D_STB_O", 1),
- Instance.Output("D_WE_O", 1),
- Instance.Output("D_CTI_O", 3),
- Instance.Output("D_LOCK_O", 1),
- Instance.Output("D_BTE_O", 1),
- Instance.Input("D_DAT_I", 32),
- Instance.Input("D_ACK_I", 1),
- Instance.Input("D_ERR_I", 1),
- Instance.Input("D_RTY_I", 1),
+ Instance.Input("interrupt", self.interrupt),
+ #Instance.Input("ext_break", self.ext_break),
+
+ Instance.Output("I_ADR_O", self._i_adr_o),
+ Instance.Output("I_DAT_O", i.dat_w),
+ Instance.Output("I_SEL_O", i.sel),
+ Instance.Output("I_CYC_O", i.cyc),
+ Instance.Output("I_STB_O", i.stb),
+ Instance.Output("I_WE_O", i.we),
+ Instance.Output("I_CTI_O", i.cti),
+ Instance.Output("I_LOCK_O"),
+ Instance.Output("I_BTE_O", i.bte),
+ Instance.Input("I_DAT_I", i.dat_r),
+ Instance.Input("I_ACK_I", i.ack),
+ Instance.Input("I_ERR_I", i.err),
+ Instance.Input("I_RTY_I", 0),
- name="lm32")
-
+ Instance.Output("D_ADR_O", self._d_adr_o),
+ Instance.Output("D_DAT_O", d.dat_w),
+ Instance.Output("D_SEL_O", d.sel),
+ Instance.Output("D_CYC_O", d.cyc),
+ Instance.Output("D_STB_O", d.stb),
+ Instance.Output("D_WE_O", d.we),
+ Instance.Output("D_CTI_O", d.cti),
+ Instance.Output("D_LOCK_O"),
+ Instance.Output("D_BTE_O", d.bte),
+ Instance.Input("D_DAT_I", d.dat_r),
+ Instance.Input("D_ACK_I", d.ack),
+ Instance.Input("D_ERR_I", d.err),
+ Instance.Input("D_RTY_I", 0))
+
def get_fragment(self):
- return Fragment(instances=[self.inst])
+ comb = [
+ self.ibus.adr.eq(self._i_adr_o[2:]),
+ self.dbus.adr.eq(self._d_adr_o[2:])
+ ]
+ return Fragment(comb=comb, specials={self._inst})
cpus = [LM32() for i in range(4)]
frag = Fragment()
for cpu in cpus:
frag += cpu.get_fragment()
-print(verilog.convert(frag, set([cpus[0].inst.get_io("interrupt"), cpus[0].inst.get_io("I_WE_O")])))
+print(verilog.convert(frag, {cpus[0].interrupt}))
@@ -1,11 +1,12 @@
-from migen.fhdl.structure import *
+from migen.fhdl.structure import Fragment
+from migen.fhdl.specials import Memory
from migen.fhdl import verilog
mem = Memory(32, 100, init=[5, 18, 32])
p1 = mem.get_port(write_capable=True, we_granularity=8)
p2 = mem.get_port(has_re=True, clock_domain="rd")
-f = Fragment(memories=[mem])
+f = Fragment(specials={mem})
v = verilog.convert(f, ios={p1.adr, p1.dat_r, p1.we, p1.dat_w,
p2.adr, p2.dat_r, p2.re})
print(v)
@@ -1,4 +1,5 @@
from migen.fhdl.structure import *
+from migen.fhdl.specials import Tristate
from migen.fhdl import verilog
n = 6
@@ -7,5 +8,5 @@
oe = Signal()
i = Signal(n)
-f = Fragment(tristates={Tristate(pad, o, oe, i)})
+f = Fragment(specials={Tristate(pad, o, oe, i)})
print(verilog.convert(f, ios={pad, o, oe, i}))
@@ -7,6 +7,7 @@
from migen.pytholite.transel import Register
from migen.pytholite.compiler import make_pytholite
from migen.sim.generic import Simulator
+from migen.fhdl.specials import Memory
from migen.fhdl import verilog
layout = [("r", 32)]
@@ -2,6 +2,7 @@
# License: GPLv3 with additional permissions (see README).
from migen.fhdl.structure import *
+from migen.fhdl.specials import Memory
from migen.sim.generic import Simulator
class Mem:
@@ -24,7 +25,7 @@ def do_simulation(self, s):
s.interrupt = True
def get_fragment(self):
- return Fragment(memories=[self.mem], sim=[self.do_simulation])
+ return Fragment(specials={self.mem}, sim=[self.do_simulation])
def main():
dut = Mem()
@@ -1,6 +1,7 @@
# Simple Processor Interface
from migen.fhdl.structure import *
+from migen.fhdl.specials import Memory
from migen.bank.description import *
from migen.flow.actor import *
@@ -117,4 +118,4 @@ def get_fragment(self):
self._reg_rd.field.w.eq(rp.dat_r)
]
- return Fragment(comb, memories=[mem])
+ return Fragment(comb, specials={mem})
View
@@ -1,4 +1,5 @@
from migen.fhdl.structure import *
+from migen.fhdl.specials import Memory
from migen.bus.simple import *
from migen.bus.transactions import *
from migen.sim.generic import PureSimulable
@@ -97,4 +98,4 @@ def get_fragment(self):
pv = self._page.field.r
comb.append(port.adr.eq(Cat(self.bus.adr[:len(port.adr)-len(pv)], pv)))
- return Fragment(comb, sync, memories=[self.mem])
+ return Fragment(comb, sync, specials={self.mem})
@@ -1,4 +1,5 @@
from migen.fhdl.structure import *
+from migen.fhdl.specials import Memory
from migen.corelogic import roundrobin
from migen.corelogic.misc import optree
from migen.bus.simple import *
@@ -228,4 +229,4 @@ def get_fragment(self):
self.bus.ack.eq(1)
)
]
- return Fragment(comb, sync, memories=[self.mem])
+ return Fragment(comb, sync, specials={self.mem})
@@ -1,5 +1,6 @@
-from migen.bus import wishbone
from migen.fhdl.structure import *
+from migen.fhdl.specials import Memory
+from migen.bus import wishbone
from migen.corelogic.fsm import FSM
from migen.corelogic.misc import split, displacer, chooser
from migen.corelogic.record import Record
@@ -136,5 +137,5 @@ def get_fragment(self):
fsm.next_state(fsm.TEST_HIT)
)
- return Fragment(comb, sync, memories=[data_mem, tag_mem]) \
+ return Fragment(comb, sync, specials={data_mem, tag_mem}) \
+ fsm.get_fragment()
View
@@ -131,13 +131,10 @@ def __init__(self, pnd):
self.pnd = pnd
def get_name(self, sig):
- if isinstance(sig, Memory):
- sig_name = "mem"
+ if sig.name_override is not None:
+ sig_name = sig.name_override
else:
- if sig.name_override is not None:
- sig_name = sig.name_override
- else:
- sig_name = self.pnd[sig]
+ sig_name = self.pnd[sig]
try:
n = self.sigs[sig]
except KeyError:
Oops, something went wrong.

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