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fhdl/specials/Instance: _printintbool -> verilog_printexpr

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commit 55ab01f928a6d531d5576853e808563fd5ed0582 1 parent c2d54f4
Sébastien Bourdeauducq authored February 24, 2013

Showing 1 changed file with 1 addition and 1 deletion. Show diff stats Hide diff stats

  1. 2  migen/fhdl/specials.py
2  migen/fhdl/specials.py
@@ -127,7 +127,7 @@ def emit_verilog(instance, ns, clock_domains):
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 				firstp = False
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 				r += "\t." + p.name + "("
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 				if isinstance(p.value, (int, bool)):
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-					r += _printintbool(p.value)[0]
  130
+					r += verilog_printexpr(ns, p.value)[0]
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 				elif isinstance(p.value, float):
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 					r += str(p.value)
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 				elif isinstance(p.value, str):

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