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fhdl/specials/Instance: _printintbool -> verilog_printexpr

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commit 55ab01f928a6d531d5576853e808563fd5ed0582 1 parent c2d54f4
Sébastien Bourdeauducq sbourdeauducq authored
Showing with 1 addition and 1 deletion.
  1. +1 −1  migen/fhdl/specials.py
2  migen/fhdl/specials.py
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@@ -127,7 +127,7 @@ def emit_verilog(instance, ns, clock_domains):
firstp = False
r += "\t." + p.name + "("
if isinstance(p.value, (int, bool)):
- r += _printintbool(p.value)[0]
+ r += verilog_printexpr(ns, p.value)[0]
elif isinstance(p.value, float):
r += str(p.value)
elif isinstance(p.value, str):
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