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fhdl/specials: clean up clock domain handling

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commit 574becc1fcb647e63e0730eb87ae4c5365622478 1 parent 77a0f0a
Sébastien Bourdeauducq authored March 26, 2013
25  migen/fhdl/specials.py
@@ -45,7 +45,7 @@ def iter_expressions(self):
45 45
 			yield self, attr, target_context
46 46
 
47 47
 	@staticmethod
48  
-	def emit_verilog(tristate, ns, clock_domains):
  48
+	def emit_verilog(tristate, ns):
49 49
 		def pe(e):
50 50
 			return verilog_printexpr(ns, e)[0]
51 51
 		w, s = value_bits_sign(tristate.target)
@@ -109,7 +109,7 @@ def iter_expressions(self):
109 109
 				yield item, "expr", SPECIAL_INOUT
110 110
 
111 111
 	@staticmethod
112  
-	def emit_verilog(instance, ns, clock_domains):
  112
+	def emit_verilog(instance, ns):
113 113
 		r = instance.of + " "
114 114
 		parameters = list(filter(lambda i: isinstance(i, Instance.Parameter), instance.items))
115 115
 		if parameters:
@@ -161,7 +161,7 @@ def __init__(self, adr, dat_r, we=None, dat_w=None,
161 161
 		self.re = re
162 162
 		self.we_granularity = we_granularity
163 163
 		self.mode = mode
164  
-		self.clock_domain = clock_domain
  164
+		self.clock = ClockSignal(clock_domain)
165 165
 
166 166
 class Memory(Special):
167 167
 	def __init__(self, width, depth, init=None, name=None):
@@ -205,21 +205,12 @@ def iter_expressions(self):
205 205
 			  ("we", SPECIAL_INPUT),
206 206
 			  ("dat_w", SPECIAL_INPUT),
207 207
 			  ("re", SPECIAL_INPUT),
208  
-			  ("dat_r", SPECIAL_OUTPUT)]:
  208
+			  ("dat_r", SPECIAL_OUTPUT),
  209
+			  ("clock", SPECIAL_INPUT)]:
209 210
 				yield p, attr, target_context
210 211
 
211  
-	def rename_clock_domain(self, old, new):
212  
-		# port expressions are always signals - no need to call Special.rename_clock_domain
213  
-		for port in self.ports:
214  
-			if port.clock_domain == old:
215  
-				port.clock_domain = new
216  
-
217  
-	def list_clock_domains(self):
218  
-		# port expressions are always signals - no need to call Special.list_clock_domains
219  
-		return set(port.clock_domain for port in self.ports)
220  
-
221 212
 	@staticmethod
222  
-	def emit_verilog(memory, ns, clock_domains):
  213
+	def emit_verilog(memory, ns):
223 214
 		r = ""
224 215
 		gn = ns.get_name # usable instead of verilog_printexpr as ports contain only signals
225 216
 		adrbits = bits_for(memory.depth-1)
@@ -244,7 +235,7 @@ def emit_verilog(memory, ns, clock_domains):
244 235
 					data_regs[id(port)] = data_reg
245 236
 
246 237
 		for port in memory.ports:
247  
-			r += "always @(posedge " + gn(clock_domains[port.clock_domain].clk) + ") begin\n"
  238
+			r += "always @(posedge " + gn(port.clock) + ") begin\n"
248 239
 			if port.we is not None:
249 240
 				if port.we_granularity:
250 241
 					n = memory.width//port.we_granularity
@@ -299,7 +290,7 @@ def __init__(self, template, **signals):
299 290
 		self.signals = signals
300 291
 
301 292
 	@staticmethod
302  
-	def emit_verilog(directive, ns, clock_domains):
  293
+	def emit_verilog(directive, ns):
303 294
 		name_dict = dict((k, ns.get_name(sig)) for k, sig in directive.signals.items())
304 295
 		formatted = directive.template.format(**name_dict)
305 296
 		return "// synthesis " + formatted + "\n"
6  migen/fhdl/verilog.py
@@ -233,10 +233,10 @@ def _lower_specials(overrides, specials):
233 233
 			lowered_specials.add(special)
234 234
 	return f, lowered_specials
235 235
 
236  
-def _printspecials(overrides, specials, ns, clock_domains):
  236
+def _printspecials(overrides, specials, ns):
237 237
 	r = ""
238 238
 	for special in sorted(specials, key=lambda x: x.huid):
239  
-		pr = _call_special_classmethod(overrides, special, "emit_verilog", ns, clock_domains)
  239
+		pr = _call_special_classmethod(overrides, special, "emit_verilog", ns)
240 240
 		if pr is None:
241 241
 			raise NotImplementedError("Special " + str(special) + " failed to implement emit_verilog")
242 242
 		r += pr
@@ -289,7 +289,7 @@ def convert(f, ios=None, name="top",
289 289
 	r += _printheader(f, ios, name, ns)
290 290
 	r += _printcomb(f, ns, display_run)
291 291
 	r += _printsync(f, ns)
292  
-	r += _printspecials(special_overrides, f.specials - lowered_specials, ns, f.clock_domains)
  292
+	r += _printspecials(special_overrides, f.specials - lowered_specials, ns)
293 293
 	r += _printinit(f, ios, ns)
294 294
 	r += "endmodule\n"
295 295
 

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