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Remove ASMI

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commit 5b36f688ea5319fc927e1f5ce410a5c7fbeca7e4 1 parent faa8b7c
Sébastien Bourdeauducq authored July 16, 2013
163  migen/actorlib/dma_asmi.py
... ...
@@ -1,163 +0,0 @@
1  
-from migen.fhdl.std import *
2  
-from migen.flow.actor import *
3  
-from migen.genlib.buffers import ReorderBuffer
4  
-
5  
-class SequentialReader(Module):
6  
-	def __init__(self, port):
7  
-		assert(len(port.slots) == 1)
8  
-		self.address = Sink([("a", port.hub.aw)])
9  
-		self.data = Source([("d", port.hub.dw)])
10  
-		self.busy = Signal()
11  
-	
12  
-		###
13  
-
14  
-		sample = Signal()
15  
-		data_reg_loaded = Signal()
16  
-		data_reg = Signal(port.hub.dw)
17  
-		accept_new = Signal()
18  
-		
19  
-		# We check that len(port.slots) == 1
20  
-		# and therefore we can assume that port.ack
21  
-		# goes low until the data phase.
22  
-		
23  
-		self.comb += [
24  
-			self.busy.eq(~data_reg_loaded | ~port.ack),
25  
-			port.adr.eq(self.address.payload.a),
26  
-			port.we.eq(0),
27  
-			accept_new.eq(~data_reg_loaded | self.data.ack),
28  
-			port.stb.eq(self.address.stb & accept_new),
29  
-			self.address.ack.eq(port.ack & accept_new),
30  
-			self.data.stb.eq(data_reg_loaded),
31  
-			self.data.payload.d.eq(data_reg)
32  
-		]
33  
-		self.sync += [
34  
-			If(self.data.ack, data_reg_loaded.eq(0)),
35  
-			If(sample,
36  
-				data_reg_loaded.eq(1),
37  
-				data_reg.eq(port.dat_r)
38  
-			),
39  
-			sample.eq(port.get_call_expression())
40  
-		]
41  
-
42  
-class OOOReader(Module):
43  
-	def __init__(self, port):
44  
-		assert(len(port.slots) > 1)
45  
-		self.address = Sink([("a", port.hub.aw)])
46  
-		self.data = Source([("d", port.hub.dw)])
47  
-		self.busy = Signal() # TODO: drive busy
48  
-	
49  
-		###
50  
-
51  
-		tag_width = flen(port.tag_call)
52  
-		data_width = port.hub.dw
53  
-		depth = len(port.slots)
54  
-		rob = ReorderBuffer(tag_width, data_width, depth)
55  
-		self.submodules += rob
56  
-		
57  
-		self.comb += [
58  
-			port.adr.eq(self.address.payload.a),
59  
-			port.we.eq(0),
60  
-			port.stb.eq(self.address.stb & rob.can_issue),
61  
-			self.address.ack.eq(port.ack & rob.can_issue),
62  
-			rob.issue.eq(self.address.stb & port.ack),
63  
-			rob.tag_issue.eq(port.base + port.tag_issue),
64  
-			
65  
-			rob.data_call.eq(port.dat_r),
66  
-			
67  
-			self.data.stb.eq(rob.can_read),
68  
-			rob.read.eq(self.data.ack),
69  
-			self.data.payload.d.eq(rob.data_read)
70  
-		]
71  
-		self.sync += [
72  
-			# Data is announced one cycle in advance.
73  
-			# Register the call to synchronize it with the data signal.
74  
-			rob.call.eq(port.call),
75  
-			rob.tag_call.eq(port.tag_call)
76  
-		]
77  
-
78  
-class SequentialWriter(Module):
79  
-	def __init__(self, port):
80  
-		assert(len(port.slots) == 1)
81  
-		self.address_data = Sink([("a", port.hub.aw), ("d", port.hub.dw)])
82  
-		self.busy = Signal()
83  
-
84  
-		###
85  
-
86  
-		data_reg = Signal(port.hub.dw)
87  
-		self.comb += [
88  
-			port.adr.eq(self.address_data.payload.a),
89  
-			port.we.eq(1),
90  
-			port.stb.eq(self.address_data.stb),
91  
-			self.address_data.ack.eq(port.ack),
92  
-			port.dat_wm.eq(0)
93  
-		]
94  
-		self.sync += [
95  
-			port.dat_w.eq(0),
96  
-			If(port.get_call_expression(),
97  
-				self.busy.eq(0),
98  
-				port.dat_w.eq(data_reg)
99  
-			),
100  
-			If(self.address_data.stb & self.address_data.ack,
101  
-				self.busy.eq(1),
102  
-				data_reg.eq(self.address_data.payload.d)
103  
-			)
104  
-		]
105  
-
106  
-class _WriteSlot(Module):
107  
-	def __init__(self, port, load_data, n):
108  
-		self.busy = Signal()
109  
-
110  
-		###
111  
-
112  
-		drive_data = Signal()
113  
-		data_reg = Signal(port.hub.dw)
114  
-		self.comb += [
115  
-			If(drive_data, port.dat_w.eq(data_reg)),
116  
-			port.dat_wm.eq(0)
117  
-		]
118  
-
119  
-		self.sync += [
120  
-			drive_data.eq(0),
121  
-			If(port.get_call_expression(n),
122  
-				self.busy.eq(0),
123  
-				drive_data.eq(1)
124  
-			),
125  
-			If(port.stb & port.ack & (port.tag_issue == n),
126  
-				self.busy.eq(1),
127  
-				data_reg.eq(load_data)
128  
-			),
129  
-		]
130  
-
131  
-class OOOWriter(Module):
132  
-	def __init__(self, port):
133  
-		assert(len(port.slots) > 1)
134  
-		self.address_data = Sink([("a", port.hub.aw), ("d", port.hub.dw)])
135  
-		self.busy = Signal()
136  
-
137  
-		###
138  
-
139  
-		self.comb += [
140  
-			port.adr.eq(self.address_data.payload.a),
141  
-			port.we.eq(1),
142  
-			port.stb.eq(self.address_data.stb),
143  
-			self.address_data.ack.eq(port.ack)
144  
-		]
145  
-
146  
-		busy = 0
147  
-		for i in range(len(port.slots)):
148  
-			write_slot = _WriteSlot(port, self.address_data.payload.d, i)
149  
-			self.submodules += write_slot
150  
-			busy = busy | write_slot.busy
151  
-		self.comb += self.busy.eq(busy)
152  
-
153  
-def Reader(port):
154  
-	if len(port.slots) == 1:
155  
-		return SequentialReader(port)
156  
-	else:
157  
-		return OOOReader(port)
158  
-
159  
-def Writer(port):
160  
-	if len(port.slots) == 1:
161  
-		return SequentialWriter(port)
162  
-	else:
163  
-		return OOOWriter(port)
304  migen/bus/asmibus.py
... ...
@@ -1,304 +0,0 @@
1  
-from migen.fhdl.std import *
2  
-from migen.fhdl.module import FinalizeError
3  
-from migen.genlib.misc import optree
4  
-from migen.genlib import roundrobin
5  
-from migen.bus.transactions import *
6  
-from migen.sim.generic import Proxy
7  
-
8  
-(SLOT_EMPTY, SLOT_PENDING, SLOT_PROCESSING) = range(3)
9  
-
10  
-class Slot(Module):
11  
-	def __init__(self, aw, time):
12  
-		self.time = time
13  
-		self.state = Signal(2)
14  
-		self.we = Signal()
15  
-		self.adr = Signal(aw)
16  
-		if self.time:
17  
-			self.mature = Signal()
18  
-		
19  
-		self.allocate = Signal()
20  
-		self.allocate_we = Signal()
21  
-		self.allocate_adr = Signal(aw)
22  
-		self.process = Signal()
23  
-		self.call = Signal()
24  
-	
25  
-		###
26  
-
27  
-		self.sync += [
28  
-			If(self.allocate,
29  
-				self.state.eq(SLOT_PENDING),
30  
-				self.we.eq(self.allocate_we),
31  
-				self.adr.eq(self.allocate_adr)
32  
-			),
33  
-			If(self.process, self.state.eq(SLOT_PROCESSING)),
34  
-			If(self.call, self.state.eq(SLOT_EMPTY))
35  
-		]
36  
-		if self.time:
37  
-			counter = Signal(max=self.time+1)
38  
-			self.comb += self.mature.eq(counter == 0)
39  
-			self.sync += [
40  
-				If(self.allocate,
41  
-					counter.eq(self.time)
42  
-				).Elif(counter != 0,
43  
-					counter.eq(counter - 1)
44  
-				)
45  
-			]
46  
-
47  
-class Port(Module):
48  
-	def __init__(self, hub, base, nslots):
49  
-		self.hub = hub
50  
-		self.base = base
51  
-		self.submodules.slots = [Slot(self.hub.aw, self.hub.time) for i in range(nslots)]
52  
-		
53  
-		# request issuance
54  
-		self.adr = Signal(self.hub.aw)
55  
-		self.we = Signal()
56  
-		self.stb = Signal()
57  
-		# tag_issue is created by finalize()
58  
-		self.ack = Signal()
59  
-		
60  
-		# request completion
61  
-		self.call = Signal()
62  
-		# tag_call is created by finalize()
63  
-		self.dat_r = Signal(self.hub.dw)
64  
-		self.dat_w = Signal(self.hub.dw)
65  
-		self.dat_wm = Signal(self.hub.dw//8)
66  
-
67  
-	def do_finalize(self):
68  
-		nslots = len(self.slots)
69  
-		if nslots > 1:
70  
-			self.tag_issue = Signal(max=nslots)
71  
-		self.tag_call = Signal(self.hub.tagbits)
72  
-
73  
-		# allocate
74  
-		for s in self.slots:
75  
-			self.comb += [
76  
-				s.allocate_we.eq(self.we),
77  
-				s.allocate_adr.eq(self.adr)
78  
-			]
79  
-		choose_slot = None
80  
-		needs_tags = len(self.slots) > 1
81  
-		for n, s in reversed(list(enumerate(self.slots))):
82  
-			choose_slot = If(s.state == SLOT_EMPTY,
83  
-				s.allocate.eq(self.stb),
84  
-				self.tag_issue.eq(n) if needs_tags else None
85  
-			).Else(choose_slot)
86  
-		self.comb += choose_slot
87  
-		self.comb += self.ack.eq(optree("|", 
88  
-			[s.state == SLOT_EMPTY for s in self.slots]))
89  
-
90  
-		# call
91  
-		self.comb += [s.call.eq(self.get_call_expression(n))
92  
-			for n, s in enumerate(self.slots)]
93  
-	
94  
-	def get_call_expression(self, slotn=0):
95  
-		if not self.finalized:
96  
-			raise FinalizeError
97  
-		return self.call \
98  
-			& (self.tag_call == (self.base + slotn))
99  
-
100  
-class Hub(Module):
101  
-	def __init__(self, aw, dw, time=0):
102  
-		self.aw = aw
103  
-		self.dw = dw
104  
-		self.time = time
105  
-
106  
-		self.ports = []
107  
-		self._next_base = 0
108  
-		self.tagbits = 0
109  
-		
110  
-		self.call = Signal()
111  
-		# tag_call is created by do_finalize()
112  
-		self.dat_r = Signal(self.dw)
113  
-		self.dat_w = Signal(self.dw)
114  
-		self.dat_wm = Signal(self.dw//8)
115  
-	
116  
-	def get_port(self, nslots=1):
117  
-		if self.finalized:
118  
-			raise FinalizeError
119  
-		new_port = Port(self, self._next_base, nslots)
120  
-		self._next_base += nslots
121  
-		self.tagbits = bits_for(self._next_base-1)
122  
-		self.ports.append(new_port)
123  
-		self.submodules += new_port
124  
-		return new_port
125  
-	
126  
-	def do_finalize(self):
127  
-		self.tag_call = Signal(self.tagbits)
128  
-		for port in self.ports:
129  
-			self.comb += [
130  
-				port.call.eq(self.call),
131  
-				port.tag_call.eq(self.tag_call),
132  
-				port.dat_r.eq(self.dat_r)
133  
-			]
134  
-		self.comb += [
135  
-			self.dat_w.eq(optree("|", [port.dat_w for port in self.ports])),
136  
-			self.dat_wm.eq(optree("|", [port.dat_wm for port in self.ports]))
137  
-		]
138  
-	
139  
-	def get_slots(self):
140  
-		if not self.finalized:
141  
-			raise FinalizeError
142  
-		return sum([port.slots for port in self.ports], [])
143  
-
144  
-class Tap(Module):
145  
-	def __init__(self, hub, handler=print):
146  
-		self.hub = hub
147  
-		self.handler = handler
148  
-		self.tag_to_transaction = dict()
149  
-		self.transaction = None
150  
-	
151  
-	def do_simulation(self, s):
152  
-		hub = Proxy(s, self.hub)
153  
-		
154  
-		# Pull any data announced in the previous cycle.
155  
-		if isinstance(self.transaction, TWrite):
156  
-			self.transaction.data = hub.dat_w
157  
-			self.transaction.sel = ~hub.dat_wm
158  
-			self.handler(self.transaction)
159  
-			self.transaction = None
160  
-		if isinstance(self.transaction, TRead):
161  
-			self.transaction.data = hub.dat_r
162  
-			self.handler(self.transaction)
163  
-			self.transaction = None
164  
-		
165  
-		# Tag issue. Transaction objects are created here
166  
-		# and placed into the tag_to_transaction dictionary.
167  
-		for tag, slot in enumerate(self.hub.get_slots()):
168  
-			if s.rd(slot.allocate):
169  
-				adr = s.rd(slot.allocate_adr)
170  
-				we = s.rd(slot.allocate_we)
171  
-				if we:
172  
-					transaction = TWrite(adr)
173  
-				else:
174  
-					transaction = TRead(adr)
175  
-				transaction.latency = s.cycle_counter
176  
-				self.tag_to_transaction[tag] = transaction
177  
-		
178  
-		# Tag call.
179  
-		if hub.call:
180  
-			transaction = self.tag_to_transaction[hub.tag_call]
181  
-			transaction.latency = s.cycle_counter - transaction.latency + 1
182  
-			self.transaction = transaction
183  
-
184  
-class Initiator(Module):
185  
-	def __init__(self, generator, port):
186  
-		self.generator = generator
187  
-		self.port = port
188  
-		self.done = False
189  
-		self._exe = None
190  
-	
191  
-	def _execute(self, s, generator, port):
192  
-		while True:
193  
-			transaction = next(generator)
194  
-			transaction_start = s.cycle_counter
195  
-			if transaction is None:
196  
-				yield
197  
-			else:
198  
-				# tag phase
199  
-				s.wr(port.adr, transaction.address)
200  
-				if isinstance(transaction, TWrite):
201  
-					s.wr(port.we, 1)
202  
-				else:
203  
-					s.wr(port.we, 0)
204  
-				s.wr(port.stb, 1)
205  
-				yield
206  
-				while not s.rd(port.ack):
207  
-					yield
208  
-				if hasattr(port, "tag_issue"):
209  
-					tag = s.rd(port.tag_issue)
210  
-				else:
211  
-					tag = 0
212  
-				tag += port.base
213  
-				s.wr(port.stb, 0)
214  
-				
215  
-				# data phase
216  
-				while not (s.rd(port.call) and (s.rd(port.tag_call) == tag)):
217  
-					yield
218  
-				if isinstance(transaction, TWrite):
219  
-					s.wr(port.dat_w, transaction.data)
220  
-					s.wr(port.dat_wm, ~transaction.sel)
221  
-					yield
222  
-					s.wr(port.dat_w, 0)
223  
-					s.wr(port.dat_wm, 0)
224  
-				else:
225  
-					yield
226  
-					transaction.data = s.rd(port.dat_r)
227  
-				transaction.latency = s.cycle_counter - transaction_start - 1
228  
-	
229  
-	def do_simulation(self, s):
230  
-		if not self.done:
231  
-			if self._exe is None:
232  
-				self._exe = self._execute(s, self.generator, self.port)
233  
-			try:
234  
-				next(self._exe)
235  
-			except StopIteration:
236  
-				self.done = True
237  
-
238  
-class TargetModel:
239  
-	def __init__(self):
240  
-		self.last_slot = 0
241  
-	
242  
-	def read(self, address):
243  
-		return 0
244  
-	
245  
-	def write(self, address, data, mask):
246  
-		pass
247  
-	
248  
-	# Round-robin scheduling.
249  
-	def select_slot(self, pending_slots):
250  
-		if not pending_slots:
251  
-			return -1
252  
-		self.last_slot += 1
253  
-		if self.last_slot > max(pending_slots):
254  
-			self.last_slot = 0
255  
-		while self.last_slot not in pending_slots:
256  
-			self.last_slot += 1
257  
-		return self.last_slot
258  
-
259  
-class Target(Module):
260  
-	def __init__(self, model, hub):
261  
-		self.model = model
262  
-		self.hub = hub
263  
-		self._calling_tag = -1
264  
-		self._write_request_d = -1
265  
-		self._write_request = -1
266  
-		self._read_request = -1
267  
-	
268  
-	def do_simulation(self, s):
269  
-		slots = self.hub.get_slots()
270  
-		
271  
-		# Data I/O
272  
-		if self._write_request >= 0:
273  
-			self.model.write(self._write_request,
274  
-				s.rd(self.hub.dat_w), s.rd(self.hub.dat_wm))
275  
-		if self._read_request >= 0:
276  
-			s.wr(self.hub.dat_r, self.model.read(self._read_request))
277  
-			
278  
-		# Request pipeline
279  
-		self._read_request = -1
280  
-		self._write_request = self._write_request_d
281  
-		self._write_request_d = -1
282  
-		
283  
-		# Examine pending slots and possibly choose one.
284  
-		# Note that we do not use the SLOT_PROCESSING state here.
285  
-		# Selected slots are immediately called.
286  
-		pending_slots = set()
287  
-		for tag, slot in enumerate(slots):
288  
-			if tag != self._calling_tag and s.rd(slot.state) == SLOT_PENDING:
289  
-				pending_slots.add(tag)
290  
-		slot_to_call = self.model.select_slot(pending_slots)
291  
-		
292  
-		# Call slot.
293  
-		if slot_to_call >= 0:
294  
-			slot = slots[slot_to_call]
295  
-			s.wr(self.hub.call, 1)
296  
-			s.wr(self.hub.tag_call, slot_to_call)
297  
-			self._calling_tag = slot_to_call
298  
-			if s.rd(slot.we):
299  
-				self._write_request_d = s.rd(slot.adr)
300  
-			else:
301  
-				self._read_request = s.rd(slot.adr)
302  
-		else:
303  
-			s.wr(self.hub.call, 0)
304  
-			self._calling_tag = -1
137  migen/bus/wishbone2asmi.py
... ...
@@ -1,137 +0,0 @@
1  
-from migen.fhdl.std import *
2  
-from migen.bus import wishbone
3  
-from migen.genlib.fsm import FSM, NextState
4  
-from migen.genlib.misc import split, displacer, chooser
5  
-from migen.genlib.record import Record, layout_len
6  
-
7  
-# cachesize (in 32-bit words) is the size of the data store, must be a power of 2
8  
-class WB2ASMI:
9  
-	def __init__(self, cachesize, asmiport):
10  
-		self.wishbone = wishbone.Interface()
11  
-		self.cachesize = cachesize
12  
-		self.asmiport = asmiport
13  
-		if len(self.asmiport.slots) != 1:
14  
-			raise ValueError("ASMI port must have 1 slot")
15  
-		if self.asmiport.hub.dw <= 32:
16  
-			raise ValueError("ASMI data width must be strictly larger than 32")
17  
-		if (self.asmiport.hub.dw % 32) != 0:
18  
-			raise ValueError("ASMI data width must be a multiple of 32")
19  
-
20  
-	def get_fragment(self):
21  
-		comb = []
22  
-		sync = []
23  
-		
24  
-		aaw = self.asmiport.hub.aw
25  
-		adw = self.asmiport.hub.dw
26  
-		
27  
-		# Split address:
28  
-		# TAG | LINE NUMBER | LINE OFFSET
29  
-		offsetbits = log2_int(adw//32)
30  
-		addressbits = aaw + offsetbits
31  
-		linebits = log2_int(self.cachesize) - offsetbits
32  
-		tagbits = addressbits - linebits
33  
-		adr_offset, adr_line, adr_tag = split(self.wishbone.adr, offsetbits, linebits, tagbits)
34  
-		
35  
-		# Data memory
36  
-		data_mem = Memory(adw, 2**linebits)
37  
-		data_port = data_mem.get_port(write_capable=True, we_granularity=8)
38  
-		
39  
-		write_from_asmi = Signal()
40  
-		write_to_asmi = Signal()
41  
-		adr_offset_r = Signal(offsetbits)
42  
-		comb += [
43  
-			data_port.adr.eq(adr_line),
44  
-			If(write_from_asmi,
45  
-				data_port.dat_w.eq(self.asmiport.dat_r),
46  
-				data_port.we.eq(Replicate(1, adw//8))
47  
-			).Else(
48  
-				data_port.dat_w.eq(Replicate(self.wishbone.dat_w, adw//32)),
49  
-				If(self.wishbone.cyc & self.wishbone.stb & self.wishbone.we & self.wishbone.ack,
50  
-					displacer(self.wishbone.sel, adr_offset, data_port.we, 2**offsetbits, reverse=True)
51  
-				)
52  
-			),
53  
-			If(write_to_asmi, self.asmiport.dat_w.eq(data_port.dat_r)),
54  
-			self.asmiport.dat_wm.eq(0),
55  
-			chooser(data_port.dat_r, adr_offset_r, self.wishbone.dat_r, reverse=True)
56  
-		]
57  
-		sync += [
58  
-			adr_offset_r.eq(adr_offset)
59  
-		]
60  
-		
61  
-		# Tag memory
62  
-		tag_layout = [("tag", tagbits), ("dirty", 1)]
63  
-		tag_mem = Memory(layout_len(tag_layout), 2**linebits)
64  
-		tag_port = tag_mem.get_port(write_capable=True)
65  
-		tag_do = Record(tag_layout)
66  
-		tag_di = Record(tag_layout)
67  
-		comb += [
68  
-			tag_do.raw_bits().eq(tag_port.dat_r),
69  
-			tag_port.dat_w.eq(tag_di.raw_bits())
70  
-		]
71  
-			
72  
-		comb += [
73  
-			tag_port.adr.eq(adr_line),
74  
-			tag_di.tag.eq(adr_tag),
75  
-			self.asmiport.adr.eq(Cat(adr_line, tag_do.tag))
76  
-		]
77  
-		
78  
-		# Control FSM
79  
-		write_to_asmi_pre = Signal()
80  
-		sync.append(write_to_asmi.eq(write_to_asmi_pre))
81  
-		
82  
-		fsm = FSM()
83  
-		
84  
-		fsm.act("IDLE",
85  
-			If(self.wishbone.cyc & self.wishbone.stb, NextState("TEST_HIT"))
86  
-		)
87  
-		fsm.act("TEST_HIT",
88  
-			If(tag_do.tag == adr_tag,
89  
-				self.wishbone.ack.eq(1),
90  
-				If(self.wishbone.we,
91  
-					tag_di.dirty.eq(1),
92  
-					tag_port.we.eq(1)
93  
-				),
94  
-				NextState("IDLE")
95  
-			).Else(
96  
-				If(tag_do.dirty,
97  
-					NextState("EVICT_ISSUE")
98  
-				).Else(
99  
-					NextState("REFILL_WRTAG")
100  
-				)
101  
-			)
102  
-		)
103  
-		
104  
-		fsm.act("EVICT_ISSUE",
105  
-			self.asmiport.stb.eq(1),
106  
-			self.asmiport.we.eq(1),
107  
-			If(self.asmiport.ack, NextState("EVICT_WAIT"))
108  
-		)
109  
-		fsm.act("EVICT_WAIT",
110  
-			# Data is actually sampled by the memory controller in the next state.
111  
-			# But since the data memory has one cycle latency, it gets the data
112  
-			# at the address given during this cycle.
113  
-			If(self.asmiport.get_call_expression(),
114  
-				write_to_asmi_pre.eq(1),
115  
-				NextState("REFILL_WRTAG")
116  
-			)
117  
-		)
118  
-		
119  
-		fsm.act("REFILL_WRTAG",
120  
-			# Write the tag first to set the ASMI address
121  
-			tag_port.we.eq(1),
122  
-			NextState("REFILL_ISSUE")
123  
-		)
124  
-		fsm.act("REFILL_ISSUE",
125  
-			self.asmiport.stb.eq(1),
126  
-			If(self.asmiport.ack, NextState("REFILL_WAIT"))
127  
-		)
128  
-		fsm.act("REFILL_WAIT",
129  
-			If(self.asmiport.get_call_expression(), NextState("REFILL_COMPLETE"))
130  
-		)
131  
-		fsm.act("REFILL_COMPLETE",
132  
-			write_from_asmi.eq(1),
133  
-			NextState("TEST_HIT")
134  
-		)
135  
-		
136  
-		return Fragment(comb, sync, specials={data_mem, tag_mem, data_port, tag_port}) \
137  
-			+ fsm.get_fragment()

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