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wishbone: arbiter

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commit 5c7131dc86f6ea84a66e37c4371ca3b1c902704d 1 parent c1041b9
Sébastien Bourdeauducq sbourdeauducq authored
Showing with 33 additions and 1 deletion.
  1. +33 −1 migen/bus/wishbone.py
34 migen/bus/wishbone.py
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@@ -1,5 +1,7 @@
from migen.fhdl import structure as f
-from .simple import Simple
+from migen.corelogic import roundrobin, multimux
+from .simple import Simple, GetSigName
+from functools import partial
_desc = [
(True, "adr", 32),
@@ -22,3 +24,33 @@ def __init__(self, name=""):
class Slave(Simple):
def __init__(self, name=""):
Simple.__init__(self, _desc, True, name)
+
+class Arbiter:
+ def __init__(self, masters, target):
+ self.masters = masters
+ self.target = target
+ self.rr = roundrobin.Inst(len(self.masters))
+
+ def GetFragment(self):
+ comb = []
+
+ # mux master->slave signals
+ m2s_names = [GetSigName(x, False) for x in _desc if x[0]]
+ m2s_masters = [[getattr(m, name) for name in m2s_names] for m in self.masters]
+ m2s_target = [getattr(self.target, name) for name in m2s_names]
+ comb += multimux.MultiMux(self.rr.grant, m2s_masters, m2s_target)
+
+ # connect slave->master signals
+ s2m_names = [GetSigName(x, False) for x in _desc if not x[0]]
+ for name in s2m_names:
+ source = getattr(self.target, name)
+ for m in self.masters:
+ dest = getattr(m, name)
+ comb.append(f.Assign(dest, source))
+
+ # connect bus requests to round-robin selector
+ reqs = [m.cyc_o for m in self.masters]
+ comb.append(f.Assign(self.rr.request, f.Cat(*reqs)))
+
+ return f.Fragment(comb) + self.rr.GetFragment()
+
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