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fhdl/verilog: do not attempt to initialize instance and mem output si…

…gnals
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1 parent 6e3b25e commit 623e8e436a4bf044a3cc0ac35e338650b6a90d3a @sbourdeauducq sbourdeauducq committed Apr 2, 2012
Showing with 6 additions and 2 deletions.
  1. +6 −2 migen/fhdl/verilog.py
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8 migen/fhdl/verilog.py
@@ -220,9 +220,13 @@ def _printmemories(f, ns, handler, clk):
r += handler(memory, ns, clk)
return r
-def _printinit(f, exclude, ns):
+def _printinit(f, ios, ns):
r = ""
- signals = list_signals(f) - exclude - list_targets(f)
+ signals = list_signals(f) \
+ - ios \
+ - list_targets(f) \
+ - list_inst_ios(f, False, True, False) \
+ - list_mem_ios(f, False, True)
if signals:
r += "initial begin\n"
for s in signals:

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