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bus/wishbone2asmi: fix cache tag size

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1 parent 0bea1e2 commit 68cd445662c8d015ff4ec9a65e8e68e3427d366d @sbourdeauducq sbourdeauducq committed
Showing with 2 additions and 2 deletions.
  1. +2 −2 migen/bus/wishbone2asmi.py
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4 migen/bus/wishbone2asmi.py
@@ -29,7 +29,7 @@ def get_fragment(self):
offsetbits = log2_int(adw//32)
addressbits = aaw + offsetbits
linebits = log2_int(self.cachesize) - offsetbits
- tagbits = aaw - linebits
+ tagbits = addressbits - linebits
adr_offset, adr_line, adr_tag = split(self.wishbone.adr, offsetbits, linebits, tagbits)
# Data memory
@@ -63,7 +63,7 @@ def get_fragment(self):
]
# Tag memory
- tag_layout = [("tag", BV(linebits)), ("dirty", BV(1))]
+ tag_layout = [("tag", BV(tagbits)), ("dirty", BV(1))]
tag_do = Record(tag_layout)
tag_do_raw = tag_do.to_signal(comb, False)
tag_di = Record(tag_layout)

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