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fhdl/verilog: tristate outputs are always wire

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commit 6fa30053bf1b247007426e61bee1a286f0226390 1 parent 9b4ca98
Sébastien Bourdeauducq authored March 06, 2013

Showing 1 changed file with 3 additions and 3 deletions. Show diff stats Hide diff stats

  1. 6  migen/fhdl/verilog.py
6  migen/fhdl/verilog.py
@@ -135,10 +135,10 @@ def _list_comb_wires(f):
135 135
 
136 136
 def _printheader(f, ios, name, ns):
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 	sigs = list_signals(f) | list_special_ios(f, True, True, True)
138  
-	it_mem_outs = list_special_ios(f, False, True, False)
  138
+	special_outs = list_special_ios(f, False, True, True)
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 	inouts = list_special_ios(f, False, False, True)
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-	targets = list_targets(f) | it_mem_outs
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-	wires = _list_comb_wires(f) | it_mem_outs
  140
+	targets = list_targets(f) | special_outs
  141
+	wires = _list_comb_wires(f) | special_outs
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 	r = "module " + name + "(\n"
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 	firstp = True
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 	for sig in sorted(ios, key=lambda x: x.huid):

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