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New migen.fhdl.std to simplify imports + len->flen

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1 parent 5208baa commit 70ffe86356f927460094fee2a57afc06177cc0c3 @sbourdeauducq sbourdeauducq committed May 22, 2013
Showing with 217 additions and 258 deletions.
  1. +1 −3 examples/basic/arrays.py
  2. +1 −1 examples/basic/complex.py
  3. +1 −2 examples/basic/fsm.py
  4. +1 −1 examples/basic/graycounter.py
  5. +1 −2 examples/basic/local_cd.py
  6. +1 −3 examples/basic/memory.py
  7. +1 −2 examples/basic/namer.py
  8. +1 −1 examples/basic/psync.py
  9. +1 −2 examples/basic/record.py
  10. +1 −2 examples/basic/simple_gpio.py
  11. +4 −9 examples/basic/tristate.py
  12. +1 −1 examples/basic/two_dividers.py
  13. +1 −1 examples/dataflow/dma.py
  14. +1 −2 examples/pytholite/uio.py
  15. +1 −5 examples/sim/abstract_transactions.py
  16. +1 −1 examples/sim/basic1.py
  17. +1 −1 examples/sim/basic2.py
  18. +1 −1 examples/sim/dataflow.py
  19. +1 −2 examples/sim/fir.py
  20. +1 −2 examples/sim/memory.py
  21. +2 −3 migen/actorlib/dma_asmi.py
  22. +1 −2 migen/actorlib/dma_wishbone.py
  23. +1 −2 migen/actorlib/misc.py
  24. +1 −2 migen/actorlib/sim.py
  25. +3 −4 migen/actorlib/spi.py
  26. +2 −3 migen/actorlib/structuring.py
  27. +1 −2 migen/bank/csrgen.py
  28. +1 −3 migen/bank/description.py
  29. +1 −2 migen/bank/eventmanager.py
  30. +2 −2 migen/bus/asmibus.py
  31. +3 −5 migen/bus/csr.py
  32. +1 −2 migen/bus/dfi.py
  33. +1 −1 migen/bus/memory.py
  34. +1 −1 migen/bus/transactions.py
  35. +3 −5 migen/bus/wishbone.py
  36. +1 −2 migen/bus/wishbone2asmi.py
  37. +6 −6 migen/bus/wishbone2csr.py
  38. +102 −0 migen/fhdl/size.py
  39. +1 −0 migen/fhdl/specials.py
  40. +4 −0 migen/fhdl/std.py
  41. +10 −106 migen/fhdl/structure.py
  42. +1 −0 migen/fhdl/tools.py
  43. +4 −3 migen/fhdl/verilog.py
  44. +1 −2 migen/flow/actor.py
  45. +1 −2 migen/flow/hooks.py
  46. +1 −2 migen/flow/isd.py
  47. +1 −1 migen/flow/network.py
  48. +1 −2 migen/flow/plumbing.py
  49. +1 −1 migen/genlib/buffers.py
  50. +2 −2 migen/genlib/cdc.py
  51. +1 −1 migen/genlib/complex.py
  52. +5 −9 migen/genlib/divider.py
  53. +2 −4 migen/genlib/fifo.py
  54. +1 −1 migen/genlib/fsm.py
  55. +1 −2 migen/genlib/ioo.py
  56. +5 −5 migen/genlib/misc.py
  57. +1 −1 migen/genlib/record.py
  58. +12 −12 migen/genlib/roundrobin.py
  59. +1 −2 migen/pytholite/io.py
  60. +1 −2 migen/pytholite/reg.py
  61. +3 −7 migen/sim/generic.py
@@ -1,6 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Instance
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.fhdl import verilog
class Example(Module):
@@ -1,4 +1,4 @@
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.genlib.complex import *
from migen.fhdl import verilog
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.fhdl import verilog
from migen.genlib.fsm import FSM
@@ -1,6 +1,6 @@
from random import Random
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.genlib.cdc import GrayCounter
from migen.sim.generic import Simulator
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.fhdl import verilog
from migen.genlib.divider import Divider
@@ -1,6 +1,4 @@
-from migen.fhdl.structure import Fragment
-from migen.fhdl.specials import Memory
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.fhdl import verilog
class Example(Module):
@@ -1,6 +1,5 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
from migen.fhdl import verilog
-from migen.fhdl.module import Module
from migen.genlib.misc import optree
def gen_list(n):
@@ -1,4 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
from migen.fhdl.specials import SynthesisDirective
from migen.fhdl import verilog
from migen.genlib.cdc import *
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.fhdl import verilog
from migen.genlib.record import *
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.fhdl import verilog
from migen.genlib.cdc import MultiReg
from migen.bank import description, csrgen
@@ -1,16 +1,11 @@
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Tristate
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.fhdl import verilog
class Example(Module):
def __init__(self, n=6):
self.pad = Signal(n)
- self.o = Signal(n)
- self.oe = Signal()
- self.i = Signal(n)
-
- self.specials += Tristate(self.pad, self.o, self.oe, self.i)
+ self.t = TSTriple(n)
+ self.specials += self.t.get_tristate(self.pad)
e = Example()
-print(verilog.convert(e, ios={e.pad, e.o, e.oe, e.i}))
+print(verilog.convert(e, ios={e.pad, e.t.o, e.t.oe, e.t.i}))
@@ -1,5 +1,5 @@
+from migen.fhdl.std import *
from migen.fhdl import verilog
-from migen.fhdl.module import Module
from migen.genlib import divider
class Example(Module):
@@ -1,6 +1,6 @@
from random import Random
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.flow.network import *
from migen.flow.transactions import *
from migen.actorlib import dma_wishbone, dma_asmi
@@ -7,8 +7,7 @@
from migen.pytholite.transel import Register
from migen.pytholite.compiler import Pytholite
from migen.sim.generic import Simulator
-from migen.fhdl.module import Module
-from migen.fhdl.specials import Memory
+from migen.fhdl.std import *
from migen.fhdl import verilog
layout = [("r", 32)]
@@ -1,10 +1,6 @@
-# Copyright (C) 2012 Vermeer Manufacturing Co.
-# License: GPLv3 with additional permissions (see README).
-
from random import Random
-from migen.fhdl.structure import *
-from migen.fhdl import autofragment
+from migen.fhdl.std import *
from migen.bus.transactions import *
from migen.bus import wishbone, asmibus
from migen.sim.generic import Simulator
@@ -1,7 +1,7 @@
# Copyright (C) 2012 Vermeer Manufacturing Co.
# License: GPLv3 with additional permissions (see README).
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
from migen.sim.generic import Simulator
# Our simple counter, which increments at every cycle
@@ -1,7 +1,7 @@
# Copyright (C) 2012 Vermeer Manufacturing Co.
# License: GPLv3 with additional permissions (see README).
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
from migen.sim.generic import Simulator, TopLevel
# A slightly improved counter.
@@ -1,4 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
from migen.flow.actor import *
from migen.flow.transactions import *
from migen.flow.network import *
View
@@ -5,8 +5,7 @@
from scipy import signal
import matplotlib.pyplot as plt
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.fhdl import verilog
from migen.genlib.misc import optree
from migen.sim.generic import Simulator
@@ -1,8 +1,7 @@
# Copyright (C) 2012 Vermeer Manufacturing Co.
# License: GPLv3 with additional permissions (see README).
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Memory
+from migen.fhdl.std import *
from migen.sim.generic import Simulator
class Mem:
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.flow.actor import *
from migen.genlib.buffers import ReorderBuffer
@@ -49,7 +48,7 @@ def __init__(self, port):
###
- tag_width = len(port.tag_call)
+ tag_width = flen(port.tag_call)
data_width = port.hub.dw
depth = len(port.slots)
rob = ReorderBuffer(tag_width, data_width, depth)
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.bus import wishbone
from migen.flow.actor import *
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.genlib.record import *
from migen.genlib.fsm import *
from migen.flow.actor import *
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.flow.actor import *
from migen.flow.transactions import *
@@ -1,7 +1,6 @@
# Simple Processor Interface
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Memory
+from migen.fhdl.std import *
from migen.bank.description import *
from migen.flow.actor import *
from migen.flow.network import *
@@ -130,8 +129,8 @@ def get_csrs(self):
class DMAReadController(_DMAController):
def __init__(self, bus_accessor, *args, **kwargs):
- bus_aw = len(bus_accessor.address.payload.a)
- bus_dw = len(bus_accessor.data.payload.d)
+ bus_aw = flen(bus_accessor.address.payload.a)
+ bus_dw = flen(bus_accessor.data.payload.d)
_DMAController.__init__(self, bus_accessor, bus_aw, bus_dw, *args, **kwargs)
g = DataFlowGraph()
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.flow.actor import *
def _rawbits_layout(l):
@@ -22,7 +21,7 @@ def __init__(self, layout_from, layout_to, reverse_from=False, reverse_to=False)
sigs_to = self.source.payload.flatten()
if reverse_to:
sigs_to = list(reversed(sigs_to))
- if sum(len(s) for s in sigs_from) != sum(len(s) for s in sigs_to):
+ if sum(flen(s) for s in sigs_from) != sum(flen(s) for s in sigs_to):
raise TypeError
self.comb += Cat(*sigs_to).eq(Cat(*sigs_from))
@@ -1,7 +1,6 @@
from operator import itemgetter
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.bus import csr
from migen.bank.description import *
@@ -1,6 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Memory
-from migen.fhdl.module import *
+from migen.fhdl.std import *
from migen.fhdl.tracer import get_obj_var_name
class _CSRBase(HUID):
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.bank.description import *
from migen.genlib.misc import optree
@@ -1,5 +1,5 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module, FinalizeError
+from migen.fhdl.std import *
+from migen.fhdl.module import FinalizeError
from migen.genlib.misc import optree
from migen.genlib import roundrobin
from migen.bus.transactions import *
View
@@ -1,6 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Memory
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.bus.transactions import *
from migen.bank.description import CSRStorage
from migen.genlib.record import *
@@ -115,10 +113,10 @@ def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
]
if self._page is None:
- self.comb += port.adr.eq(self.bus.adr[word_bits:len(port.adr)])
+ self.comb += port.adr.eq(self.bus.adr[word_bits:flen(port.adr)])
else:
pv = self._page.storage
- self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:len(port.adr)-len(pv)], pv))
+ self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:flen(port.adr)-flen(pv)], pv))
def get_csrs(self):
if self._page is None:
View
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.genlib.record import *
def phase_description(a, ba, d):
View
@@ -1,4 +1,4 @@
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.bus.transactions import *
def _byte_mask(orig, dat_w, sel):
@@ -1,4 +1,4 @@
-from migen.fhdl.structure import bits_for
+from migen.fhdl.std import *
class Transaction:
def __init__(self, address, data=0, sel=None, busname=None):
@@ -1,6 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Memory
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.genlib import roundrobin
from migen.genlib.record import *
from migen.genlib.misc import optree
@@ -91,7 +89,7 @@ def __init__(self, master, slaves, register=False):
]
# mux (1-hot) slave data return
- masked = [Replicate(slave_sel_r[i], len(master.dat_r)) & slaves[i][1].dat_r for i in range(ns)]
+ masked = [Replicate(slave_sel_r[i], flen(master.dat_r)) & slaves[i][1].dat_r for i in range(ns)]
self.comb += master.dat_r.eq(optree("|", masked))
class InterconnectShared(Module):
@@ -210,7 +208,7 @@ def __init__(self, mem_or_size, read_only=None, init=None, bus=None):
for i in range(4)]
# address and data
self.comb += [
- port.adr.eq(self.bus.adr[:len(port.adr)]),
+ port.adr.eq(self.bus.adr[:flen(port.adr)]),
self.bus.dat_r.eq(port.dat_r)
]
if not read_only:
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Memory
+from migen.fhdl.std import *
from migen.bus import wishbone
from migen.genlib.fsm import FSM
from migen.genlib.misc import split, displacer, chooser
@@ -1,23 +1,23 @@
+from migen.fhdl.std import *
from migen.bus import wishbone
from migen.bus import csr
-from migen.fhdl.structure import *
from migen.genlib.misc import timeline
-class WB2CSR:
+class WB2CSR(Module):
def __init__(self):
self.wishbone = wishbone.Interface()
self.csr = csr.Interface()
- def get_fragment(self):
- sync = [
+ ###
+
+ self.sync += [
self.csr.we.eq(0),
self.csr.dat_w.eq(self.wishbone.dat_w[:csr.data_width]),
self.csr.adr.eq(self.wishbone.adr[:14]),
self.wishbone.dat_r.eq(self.csr.dat_r)
]
- sync += timeline(self.wishbone.cyc & self.wishbone.stb, [
+ self.sync += timeline(self.wishbone.cyc & self.wishbone.stb, [
(1, [self.csr.we.eq(self.wishbone.we)]),
(2, [self.wishbone.ack.eq(1)]),
(3, [self.wishbone.ack.eq(0)])
])
- return Fragment(sync=sync)
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