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New migen.fhdl.std to simplify imports + len->flen

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commit 70ffe86356f927460094fee2a57afc06177cc0c3 1 parent 5208baa
Sébastien Bourdeauducq authored

Showing 61 changed files with 217 additions and 258 deletions. Show diff stats Hide diff stats

  1. 4  examples/basic/arrays.py
  2. 2  examples/basic/complex.py
  3. 3  examples/basic/fsm.py
  4. 2  examples/basic/graycounter.py
  5. 3  examples/basic/local_cd.py
  6. 4  examples/basic/memory.py
  7. 3  examples/basic/namer.py
  8. 2  examples/basic/psync.py
  9. 3  examples/basic/record.py
  10. 3  examples/basic/simple_gpio.py
  11. 13  examples/basic/tristate.py
  12. 2  examples/basic/two_dividers.py
  13. 2  examples/dataflow/dma.py
  14. 3  examples/pytholite/uio.py
  15. 6  examples/sim/abstract_transactions.py
  16. 2  examples/sim/basic1.py
  17. 2  examples/sim/basic2.py
  18. 2  examples/sim/dataflow.py
  19. 3  examples/sim/fir.py
  20. 3  examples/sim/memory.py
  21. 5  migen/actorlib/dma_asmi.py
  22. 3  migen/actorlib/dma_wishbone.py
  23. 3  migen/actorlib/misc.py
  24. 3  migen/actorlib/sim.py
  25. 7  migen/actorlib/spi.py
  26. 5  migen/actorlib/structuring.py
  27. 3  migen/bank/csrgen.py
  28. 4  migen/bank/description.py
  29. 3  migen/bank/eventmanager.py
  30. 4  migen/bus/asmibus.py
  31. 8  migen/bus/csr.py
  32. 3  migen/bus/dfi.py
  33. 2  migen/bus/memory.py
  34. 2  migen/bus/transactions.py
  35. 8  migen/bus/wishbone.py
  36. 3  migen/bus/wishbone2asmi.py
  37. 12  migen/bus/wishbone2csr.py
  38. 102  migen/fhdl/size.py
  39. 1  migen/fhdl/specials.py
  40. 4  migen/fhdl/std.py
  41. 116  migen/fhdl/structure.py
  42. 1  migen/fhdl/tools.py
  43. 7  migen/fhdl/verilog.py
  44. 3  migen/flow/actor.py
  45. 3  migen/flow/hooks.py
  46. 3  migen/flow/isd.py
  47. 2  migen/flow/network.py
  48. 3  migen/flow/plumbing.py
  49. 2  migen/genlib/buffers.py
  50. 4  migen/genlib/cdc.py
  51. 2  migen/genlib/complex.py
  52. 14  migen/genlib/divider.py
  53. 6  migen/genlib/fifo.py
  54. 2  migen/genlib/fsm.py
  55. 3  migen/genlib/ioo.py
  56. 10  migen/genlib/misc.py
  57. 2  migen/genlib/record.py
  58. 24  migen/genlib/roundrobin.py
  59. 3  migen/pytholite/io.py
  60. 3  migen/pytholite/reg.py
  61. 10  migen/sim/generic.py
4  examples/basic/arrays.py
... ...
@@ -1,6 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.specials import Instance
3  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
4 2
 from migen.fhdl import verilog
5 3
 
6 4
 class Example(Module):
2  examples/basic/complex.py
... ...
@@ -1,4 +1,4 @@
1  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
2 2
 from migen.genlib.complex import *
3 3
 from migen.fhdl import verilog
4 4
 
3  examples/basic/fsm.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.fhdl import verilog
4 3
 from migen.genlib.fsm import FSM
5 4
 
2  examples/basic/graycounter.py
... ...
@@ -1,6 +1,6 @@
1 1
 from random import Random
2 2
 
3  
-from migen.fhdl.module import Module
  3
+from migen.fhdl.std import *
4 4
 from migen.genlib.cdc import GrayCounter
5 5
 from migen.sim.generic import Simulator
6 6
 
3  examples/basic/local_cd.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.fhdl import verilog
4 3
 from migen.genlib.divider import Divider
5 4
 
4  examples/basic/memory.py
... ...
@@ -1,6 +1,4 @@
1  
-from migen.fhdl.structure import Fragment
2  
-from migen.fhdl.specials import Memory
3  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
4 2
 from migen.fhdl import verilog
5 3
 
6 4
 class Example(Module):
3  examples/basic/namer.py
... ...
@@ -1,6 +1,5 @@
1  
-from migen.fhdl.structure import *
  1
+from migen.fhdl.std import *
2 2
 from migen.fhdl import verilog
3  
-from migen.fhdl.module import Module
4 3
 from migen.genlib.misc import optree
5 4
 
6 5
 def gen_list(n):
2  examples/basic/psync.py
... ...
@@ -1,4 +1,4 @@
1  
-from migen.fhdl.structure import *
  1
+from migen.fhdl.std import *
2 2
 from migen.fhdl.specials import SynthesisDirective
3 3
 from migen.fhdl import verilog
4 4
 from migen.genlib.cdc import *
3  examples/basic/record.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.fhdl import verilog
4 3
 from migen.genlib.record import *
5 4
 
3  examples/basic/simple_gpio.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.fhdl import verilog
4 3
 from migen.genlib.cdc import MultiReg
5 4
 from migen.bank import description, csrgen
13  examples/basic/tristate.py
... ...
@@ -1,16 +1,11 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.specials import Tristate
3  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
4 2
 from migen.fhdl import verilog
5 3
 
6 4
 class Example(Module):
7 5
 	def __init__(self, n=6):
8 6
 		self.pad = Signal(n)
9  
-		self.o = Signal(n)
10  
-		self.oe = Signal()
11  
-		self.i = Signal(n)
12  
-
13  
-		self.specials += Tristate(self.pad, self.o, self.oe, self.i)
  7
+		self.t = TSTriple(n)
  8
+		self.specials += self.t.get_tristate(self.pad)
14 9
 
15 10
 e = Example()
16  
-print(verilog.convert(e, ios={e.pad, e.o, e.oe, e.i}))
  11
+print(verilog.convert(e, ios={e.pad, e.t.o, e.t.oe, e.t.i}))
2  examples/basic/two_dividers.py
... ...
@@ -1,5 +1,5 @@
  1
+from migen.fhdl.std import *
1 2
 from migen.fhdl import verilog
2  
-from migen.fhdl.module import Module
3 3
 from migen.genlib import divider
4 4
 
5 5
 class Example(Module):
2  examples/dataflow/dma.py
... ...
@@ -1,6 +1,6 @@
1 1
 from random import Random
2 2
 
3  
-from migen.fhdl.module import Module
  3
+from migen.fhdl.std import *
4 4
 from migen.flow.network import *
5 5
 from migen.flow.transactions import *
6 6
 from migen.actorlib import dma_wishbone, dma_asmi
3  examples/pytholite/uio.py
@@ -7,8 +7,7 @@
7 7
 from migen.pytholite.transel import Register
8 8
 from migen.pytholite.compiler import Pytholite
9 9
 from migen.sim.generic import Simulator
10  
-from migen.fhdl.module import Module
11  
-from migen.fhdl.specials import Memory
  10
+from migen.fhdl.std import *
12 11
 from migen.fhdl import verilog
13 12
 
14 13
 layout = [("r", 32)]
6  examples/sim/abstract_transactions.py
... ...
@@ -1,10 +1,6 @@
1  
-# Copyright (C) 2012 Vermeer Manufacturing Co.
2  
-# License: GPLv3 with additional permissions (see README).
3  
-
4 1
 from random import Random
5 2
 
6  
-from migen.fhdl.structure import *
7  
-from migen.fhdl import autofragment
  3
+from migen.fhdl.std import *
8 4
 from migen.bus.transactions import *
9 5
 from migen.bus import wishbone, asmibus
10 6
 from migen.sim.generic import Simulator
2  examples/sim/basic1.py
... ...
@@ -1,7 +1,7 @@
1 1
 # Copyright (C) 2012 Vermeer Manufacturing Co.
2 2
 # License: GPLv3 with additional permissions (see README).
3 3
 
4  
-from migen.fhdl.structure import *
  4
+from migen.fhdl.std import *
5 5
 from migen.sim.generic import Simulator
6 6
 
7 7
 # Our simple counter, which increments at every cycle
2  examples/sim/basic2.py
... ...
@@ -1,7 +1,7 @@
1 1
 # Copyright (C) 2012 Vermeer Manufacturing Co.
2 2
 # License: GPLv3 with additional permissions (see README).
3 3
 
4  
-from migen.fhdl.structure import *
  4
+from migen.fhdl.std import *
5 5
 from migen.sim.generic import Simulator, TopLevel
6 6
 
7 7
 # A slightly improved counter.
2  examples/sim/dataflow.py
... ...
@@ -1,4 +1,4 @@
1  
-from migen.fhdl.structure import *
  1
+from migen.fhdl.std import *
2 2
 from migen.flow.actor import *
3 3
 from migen.flow.transactions import *
4 4
 from migen.flow.network import *
3  examples/sim/fir.py
@@ -5,8 +5,7 @@
5 5
 from scipy import signal
6 6
 import matplotlib.pyplot as plt
7 7
 
8  
-from migen.fhdl.structure import *
9  
-from migen.fhdl.module import Module
  8
+from migen.fhdl.std import *
10 9
 from migen.fhdl import verilog
11 10
 from migen.genlib.misc import optree
12 11
 from migen.sim.generic import Simulator
3  examples/sim/memory.py
... ...
@@ -1,8 +1,7 @@
1 1
 # Copyright (C) 2012 Vermeer Manufacturing Co.
2 2
 # License: GPLv3 with additional permissions (see README).
3 3
 
4  
-from migen.fhdl.structure import *
5  
-from migen.fhdl.specials import Memory
  4
+from migen.fhdl.std import *
6 5
 from migen.sim.generic import Simulator
7 6
 
8 7
 class Mem:
5  migen/actorlib/dma_asmi.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.flow.actor import *
4 3
 from migen.genlib.buffers import ReorderBuffer
5 4
 
@@ -49,7 +48,7 @@ def __init__(self, port):
49 48
 	
50 49
 		###
51 50
 
52  
-		tag_width = len(port.tag_call)
  51
+		tag_width = flen(port.tag_call)
53 52
 		data_width = port.hub.dw
54 53
 		depth = len(port.slots)
55 54
 		rob = ReorderBuffer(tag_width, data_width, depth)
3  migen/actorlib/dma_wishbone.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.bus import wishbone
4 3
 from migen.flow.actor import *
5 4
 
3  migen/actorlib/misc.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.genlib.record import *
4 3
 from migen.genlib.fsm import *
5 4
 from migen.flow.actor import *
3  migen/actorlib/sim.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.flow.actor import *
4 3
 from migen.flow.transactions import *
5 4
 
7  migen/actorlib/spi.py
... ...
@@ -1,7 +1,6 @@
1 1
 # Simple Processor Interface
2 2
 
3  
-from migen.fhdl.structure import *
4  
-from migen.fhdl.specials import Memory
  3
+from migen.fhdl.std import *
5 4
 from migen.bank.description import *
6 5
 from migen.flow.actor import *
7 6
 from migen.flow.network import *
@@ -130,8 +129,8 @@ def get_csrs(self):
130 129
 
131 130
 class DMAReadController(_DMAController):
132 131
 	def __init__(self, bus_accessor, *args, **kwargs):
133  
-		bus_aw = len(bus_accessor.address.payload.a)
134  
-		bus_dw = len(bus_accessor.data.payload.d)
  132
+		bus_aw = flen(bus_accessor.address.payload.a)
  133
+		bus_dw = flen(bus_accessor.data.payload.d)
135 134
 		_DMAController.__init__(self, bus_accessor, bus_aw, bus_dw, *args, **kwargs)
136 135
 		
137 136
 		g = DataFlowGraph()
5  migen/actorlib/structuring.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.flow.actor import *
4 3
 
5 4
 def _rawbits_layout(l):
@@ -22,7 +21,7 @@ def __init__(self, layout_from, layout_to, reverse_from=False, reverse_to=False)
22 21
 		sigs_to = self.source.payload.flatten()
23 22
 		if reverse_to:
24 23
 			sigs_to = list(reversed(sigs_to))
25  
-		if sum(len(s) for s in sigs_from) != sum(len(s) for s in sigs_to):
  24
+		if sum(flen(s) for s in sigs_from) != sum(flen(s) for s in sigs_to):
26 25
 			raise TypeError
27 26
 		self.comb += Cat(*sigs_to).eq(Cat(*sigs_from))
28 27
 
3  migen/bank/csrgen.py
... ...
@@ -1,7 +1,6 @@
1 1
 from operator import itemgetter
2 2
 
3  
-from migen.fhdl.structure import *
4  
-from migen.fhdl.module import Module
  3
+from migen.fhdl.std import *
5 4
 from migen.bus import csr
6 5
 from migen.bank.description import *
7 6
 
4  migen/bank/description.py
... ...
@@ -1,6 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.specials import Memory
3  
-from migen.fhdl.module import *
  1
+from migen.fhdl.std import *
4 2
 from migen.fhdl.tracer import get_obj_var_name
5 3
 
6 4
 class _CSRBase(HUID):
3  migen/bank/eventmanager.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.bank.description import *
4 3
 from migen.genlib.misc import optree
5 4
 
4  migen/bus/asmibus.py
... ...
@@ -1,5 +1,5 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module, FinalizeError
  1
+from migen.fhdl.std import *
  2
+from migen.fhdl.module import FinalizeError
3 3
 from migen.genlib.misc import optree
4 4
 from migen.genlib import roundrobin
5 5
 from migen.bus.transactions import *
8  migen/bus/csr.py
... ...
@@ -1,6 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.specials import Memory
3  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
4 2
 from migen.bus.transactions import *
5 3
 from migen.bank.description import CSRStorage
6 4
 from migen.genlib.record import *
@@ -115,10 +113,10 @@ def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
115 113
 				]
116 114
 		
117 115
 		if self._page is None:
118  
-			self.comb += port.adr.eq(self.bus.adr[word_bits:len(port.adr)])
  116
+			self.comb += port.adr.eq(self.bus.adr[word_bits:flen(port.adr)])
119 117
 		else:
120 118
 			pv = self._page.storage
121  
-			self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:len(port.adr)-len(pv)], pv))
  119
+			self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:flen(port.adr)-flen(pv)], pv))
122 120
 
123 121
 	def get_csrs(self):
124 122
 		if self._page is None:
3  migen/bus/dfi.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.genlib.record import *
4 3
 
5 4
 def phase_description(a, ba, d):
2  migen/bus/memory.py
... ...
@@ -1,4 +1,4 @@
1  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
2 2
 from migen.bus.transactions import *
3 3
 
4 4
 def _byte_mask(orig, dat_w, sel):
2  migen/bus/transactions.py
... ...
@@ -1,4 +1,4 @@
1  
-from migen.fhdl.structure import bits_for
  1
+from migen.fhdl.std import *
2 2
 
3 3
 class Transaction:
4 4
 	def __init__(self, address, data=0, sel=None, busname=None):
8  migen/bus/wishbone.py
... ...
@@ -1,6 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.specials import Memory
3  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
4 2
 from migen.genlib import roundrobin
5 3
 from migen.genlib.record import *
6 4
 from migen.genlib.misc import optree
@@ -91,7 +89,7 @@ def __init__(self, master, slaves, register=False):
91 89
 		]
92 90
 		
93 91
 		# mux (1-hot) slave data return
94  
-		masked = [Replicate(slave_sel_r[i], len(master.dat_r)) & slaves[i][1].dat_r for i in range(ns)]
  92
+		masked = [Replicate(slave_sel_r[i], flen(master.dat_r)) & slaves[i][1].dat_r for i in range(ns)]
95 93
 		self.comb += master.dat_r.eq(optree("|", masked))
96 94
 
97 95
 class InterconnectShared(Module):
@@ -210,7 +208,7 @@ def __init__(self, mem_or_size, read_only=None, init=None, bus=None):
210 208
 				for i in range(4)]
211 209
 		# address and data
212 210
 		self.comb += [
213  
-			port.adr.eq(self.bus.adr[:len(port.adr)]),
  211
+			port.adr.eq(self.bus.adr[:flen(port.adr)]),
214 212
 			self.bus.dat_r.eq(port.dat_r)
215 213
 		]
216 214
 		if not read_only:
3  migen/bus/wishbone2asmi.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.specials import Memory
  1
+from migen.fhdl.std import *
3 2
 from migen.bus import wishbone
4 3
 from migen.genlib.fsm import FSM
5 4
 from migen.genlib.misc import split, displacer, chooser
12  migen/bus/wishbone2csr.py
... ...
@@ -1,23 +1,23 @@
  1
+from migen.fhdl.std import *
1 2
 from migen.bus import wishbone
2 3
 from migen.bus import csr
3  
-from migen.fhdl.structure import *
4 4
 from migen.genlib.misc import timeline
5 5
 
6  
-class WB2CSR:
  6
+class WB2CSR(Module):
7 7
 	def __init__(self):
8 8
 		self.wishbone = wishbone.Interface()
9 9
 		self.csr = csr.Interface()
10 10
 	
11  
-	def get_fragment(self):
12  
-		sync = [
  11
+		###
  12
+
  13
+		self.sync += [
13 14
 			self.csr.we.eq(0),
14 15
 			self.csr.dat_w.eq(self.wishbone.dat_w[:csr.data_width]),
15 16
 			self.csr.adr.eq(self.wishbone.adr[:14]),
16 17
 			self.wishbone.dat_r.eq(self.csr.dat_r)
17 18
 		]
18  
-		sync += timeline(self.wishbone.cyc & self.wishbone.stb, [
  19
+		self.sync += timeline(self.wishbone.cyc & self.wishbone.stb, [
19 20
 			(1, [self.csr.we.eq(self.wishbone.we)]),
20 21
 			(2, [self.wishbone.ack.eq(1)]),
21 22
 			(3, [self.wishbone.ack.eq(0)])
22 23
 		])
23  
-		return Fragment(sync=sync)
102  migen/fhdl/size.py
... ...
@@ -0,0 +1,102 @@
  1
+from migen.fhdl import structure as f
  2
+
  3
+def log2_int(n, need_pow2=True):
  4
+	l = 1
  5
+	r = 0
  6
+	while l < n:
  7
+		l *= 2
  8
+		r += 1
  9
+	if need_pow2 and l != n:
  10
+		raise ValueError("Not a power of 2")
  11
+	return r
  12
+
  13
+def bits_for(n, require_sign_bit=False):
  14
+	if n > 0:
  15
+		r = log2_int(n + 1, False)
  16
+	else:
  17
+		require_sign_bit = True
  18
+		r = log2_int(-n, False)
  19
+	if require_sign_bit:
  20
+		r += 1
  21
+	return r
  22
+
  23
+def value_bits_sign(v):
  24
+	if isinstance(v, bool):
  25
+		return 1, False
  26
+	elif isinstance(v, int):
  27
+		return bits_for(v), v < 0
  28
+	elif isinstance(v, f.Signal):
  29
+		return v.nbits, v.signed
  30
+	elif isinstance(v, (f.ClockSignal, f.ResetSignal)):
  31
+		return 1, False
  32
+	elif isinstance(v, f._Operator):
  33
+		obs = list(map(value_bits_sign, v.operands))
  34
+		if v.op == "+" or v.op == "-":
  35
+			if not obs[0][1] and not obs[1][1]:
  36
+				# both operands unsigned
  37
+				return max(obs[0][0], obs[1][0]) + 1, False
  38
+			elif obs[0][1] and obs[1][1]:
  39
+				# both operands signed
  40
+				return max(obs[0][0], obs[1][0]) + 1, True
  41
+			elif not obs[0][1] and obs[1][1]:
  42
+				# first operand unsigned (add sign bit), second operand signed
  43
+				return max(obs[0][0] + 1, obs[1][0]) + 1, True
  44
+			else:
  45
+				# first signed, second operand unsigned (add sign bit)
  46
+				return max(obs[0][0], obs[1][0] + 1) + 1, True
  47
+		elif v.op == "*":
  48
+			if not obs[0][1] and not obs[1][1]:
  49
+				# both operands unsigned
  50
+				return obs[0][0] + obs[1][0]
  51
+			elif obs[0][1] and obs[1][1]:
  52
+				# both operands signed
  53
+				return obs[0][0] + obs[1][0] - 1
  54
+			else:
  55
+				# one operand signed, the other unsigned (add sign bit)
  56
+				return obs[0][0] + obs[1][0] + 1 - 1
  57
+		elif v.op == "<<<":
  58
+			if obs[1][1]:
  59
+				extra = 2**(obs[1][0] - 1) - 1
  60
+			else:
  61
+				extra = 2**obs[1][0] - 1
  62
+			return obs[0][0] + extra, obs[0][1]
  63
+		elif v.op == ">>>":
  64
+			if obs[1][1]:
  65
+				extra = 2**(obs[1][0] - 1)
  66
+			else:
  67
+				extra = 0
  68
+			return obs[0][0] + extra, obs[0][1]
  69
+		elif v.op == "&" or v.op == "^" or v.op == "|":
  70
+			if not obs[0][1] and not obs[1][1]:
  71
+				# both operands unsigned
  72
+				return max(obs[0][0], obs[1][0]), False
  73
+			elif obs[0][1] and obs[1][1]:
  74
+				# both operands signed
  75
+				return max(obs[0][0], obs[1][0]), True
  76
+			elif not obs[0][1] and obs[1][1]:
  77
+				# first operand unsigned (add sign bit), second operand signed
  78
+				return max(obs[0][0] + 1, obs[1][0]), True
  79
+			else:
  80
+				# first signed, second operand unsigned (add sign bit)
  81
+				return max(obs[0][0], obs[1][0] + 1), True
  82
+		elif v.op == "<" or v.op == "<=" or v.op == "==" or v.op == "!=" \
  83
+		  or v.op == ">" or v.op == ">=":
  84
+			  return 1, False
  85
+		elif v.op == "~":
  86
+			return obs[0]
  87
+		else:
  88
+			raise TypeError
  89
+	elif isinstance(v, f._Slice):
  90
+		return v.stop - v.start, value_bits_sign(v.value)[1]
  91
+	elif isinstance(v, f.Cat):
  92
+		return sum(value_bits_sign(sv)[0] for sv in v.l), False
  93
+	elif isinstance(v, f.Replicate):
  94
+		return (value_bits_sign(v.v)[0])*v.n, False
  95
+	elif isinstance(v, f._ArrayProxy):
  96
+		bsc = map(value_bits_sign, v.choices)
  97
+		return max(bs[0] for bs in bsc), any(bs[1] for bs in bsc)
  98
+	else:
  99
+		raise TypeError
  100
+
  101
+def flen(v):
  102
+	return value_bits_sign(v)[0]
1  migen/fhdl/specials.py
... ...
@@ -1,4 +1,5 @@
1 1
 from migen.fhdl.structure import *
  2
+from migen.fhdl.size import bits_for, value_bits_sign
2 3
 from migen.fhdl.tools import *
3 4
 from migen.fhdl.tracer import get_obj_var_name
4 5
 from migen.fhdl.verilog import _printexpr as verilog_printexpr
4  migen/fhdl/std.py
... ...
@@ -0,0 +1,4 @@
  1
+from migen.fhdl.structure import *
  2
+from migen.fhdl.module import Module
  3
+from migen.fhdl.specials import TSTriple, Instance, Memory
  4
+from migen.fhdl.size import log2_int, bits_for, flen
116  migen/fhdl/structure.py
@@ -5,26 +5,6 @@
5 5
 
6 6
 from migen.fhdl import tracer
7 7
 
8  
-def log2_int(n, need_pow2=True):
9  
-	l = 1
10  
-	r = 0
11  
-	while l < n:
12  
-		l *= 2
13  
-		r += 1
14  
-	if need_pow2 and l != n:
15  
-		raise ValueError("Not a power of 2")
16  
-	return r
17  
-
18  
-def bits_for(n, require_sign_bit=False):
19  
-	if n > 0:
20  
-		r = log2_int(n + 1, False)
21  
-	else:
22  
-		require_sign_bit = True
23  
-		r = log2_int(-n, False)
24  
-	if require_sign_bit:
25  
-		r += 1
26  
-	return r
27  
-
28 8
 class HUID:
29 9
 	__next_uid = 0
30 10
 	def __init__(self):
@@ -88,19 +68,21 @@ def __ge__(self, other):
88 68
 	
89 69
 	
90 70
 	def __getitem__(self, key):
  71
+		from migen.fhdl.size import flen
  72
+
91 73
 		if isinstance(key, int):
92 74
 			if key < 0:
93  
-				key += len(self)
  75
+				key += flen(self)
94 76
 			return _Slice(self, key, key+1)
95 77
 		elif isinstance(key, slice):
96 78
 			start = key.start or 0
97  
-			stop = key.stop or len(self)
  79
+			stop = key.stop or flen(self)
98 80
 			if start < 0:
99  
-				start += len(self)
  81
+				start += flen(self)
100 82
 			if stop < 0:
101  
-				stop += len(self)
102  
-			if stop > len(self):
103  
-				stop = len(self)
  83
+				stop += flen(self)
  84
+			if stop > flen(self):
  85
+				stop = flen(self)
104 86
 			if key.step != None:
105 87
 				raise KeyError
106 88
 			return _Slice(self, start, stop)
@@ -109,9 +91,6 @@ def __getitem__(self, key):
109 91
 	
110 92
 	def eq(self, r):
111 93
 		return _Assign(self, r)
112  
-
113  
-	def __len__(self):
114  
-		return value_bits_sign(self)[0]
115 94
 	
116 95
 	def __hash__(self):
117 96
 		return HUID.__hash__(self)
@@ -142,6 +121,8 @@ def __init__(self, v, n):
142 121
 
143 122
 class Signal(Value):
144 123
 	def __init__(self, bits_sign=None, name=None, variable=False, reset=0, name_override=None, min=None, max=None):
  124
+		from migen.fhdl.size import bits_for
  125
+
145 126
 		Value.__init__(self)
146 127
 		
147 128
 		# determine number of bits and signedness
@@ -304,80 +285,3 @@ def __add__(self, other):
304 285
 			self.clock_domains + other.clock_domains,
305 286
 			self.sim + other.sim)
306 287
 
307  
-def value_bits_sign(v):
308  
-	if isinstance(v, bool):
309  
-		return 1, False
310  
-	elif isinstance(v, int):
311  
-		return bits_for(v), v < 0
312  
-	elif isinstance(v, Signal):
313  
-		return v.nbits, v.signed
314  
-	elif isinstance(v, (ClockSignal, ResetSignal)):
315  
-		return 1, False
316  
-	elif isinstance(v, _Operator):
317  
-		obs = list(map(value_bits_sign, v.operands))
318  
-		if v.op == "+" or v.op == "-":
319  
-			if not obs[0][1] and not obs[1][1]:
320  
-				# both operands unsigned
321  
-				return max(obs[0][0], obs[1][0]) + 1, False
322  
-			elif obs[0][1] and obs[1][1]:
323  
-				# both operands signed
324  
-				return max(obs[0][0], obs[1][0]) + 1, True
325  
-			elif not obs[0][1] and obs[1][1]:
326  
-				# first operand unsigned (add sign bit), second operand signed
327  
-				return max(obs[0][0] + 1, obs[1][0]) + 1, True
328  
-			else:
329  
-				# first signed, second operand unsigned (add sign bit)
330  
-				return max(obs[0][0], obs[1][0] + 1) + 1, True
331  
-		elif v.op == "*":
332  
-			if not obs[0][1] and not obs[1][1]:
333  
-				# both operands unsigned
334  
-				return obs[0][0] + obs[1][0]
335  
-			elif obs[0][1] and obs[1][1]:
336  
-				# both operands signed
337  
-				return obs[0][0] + obs[1][0] - 1
338  
-			else:
339  
-				# one operand signed, the other unsigned (add sign bit)
340  
-				return obs[0][0] + obs[1][0] + 1 - 1
341  
-		elif v.op == "<<<":
342  
-			if obs[1][1]:
343  
-				extra = 2**(obs[1][0] - 1) - 1
344  
-			else:
345  
-				extra = 2**obs[1][0] - 1
346  
-			return obs[0][0] + extra, obs[0][1]
347  
-		elif v.op == ">>>":
348  
-			if obs[1][1]:
349  
-				extra = 2**(obs[1][0] - 1)
350  
-			else:
351  
-				extra = 0
352  
-			return obs[0][0] + extra, obs[0][1]
353  
-		elif v.op == "&" or v.op == "^" or v.op == "|":
354  
-			if not obs[0][1] and not obs[1][1]:
355  
-				# both operands unsigned
356  
-				return max(obs[0][0], obs[1][0]), False
357  
-			elif obs[0][1] and obs[1][1]:
358  
-				# both operands signed
359  
-				return max(obs[0][0], obs[1][0]), True
360  
-			elif not obs[0][1] and obs[1][1]:
361  
-				# first operand unsigned (add sign bit), second operand signed
362  
-				return max(obs[0][0] + 1, obs[1][0]), True
363  
-			else:
364  
-				# first signed, second operand unsigned (add sign bit)
365  
-				return max(obs[0][0], obs[1][0] + 1), True
366  
-		elif v.op == "<" or v.op == "<=" or v.op == "==" or v.op == "!=" \
367  
-		  or v.op == ">" or v.op == ">=":
368  
-			  return 1, False
369  
-		elif v.op == "~":
370  
-			return obs[0]
371  
-		else:
372  
-			raise TypeError
373  
-	elif isinstance(v, _Slice):
374  
-		return v.stop - v.start, value_bits_sign(v.value)[1]
375  
-	elif isinstance(v, Cat):
376  
-		return sum(value_bits_sign(sv)[0] for sv in v.l), False
377  
-	elif isinstance(v, Replicate):
378  
-		return (value_bits_sign(v.v)[0])*v.n, False
379  
-	elif isinstance(v, _ArrayProxy):
380  
-		bsc = map(value_bits_sign, v.choices)
381  
-		return max(bs[0] for bs in bsc), any(bs[1] for bs in bsc)
382  
-	else:
383  
-		raise TypeError
1  migen/fhdl/tools.py
@@ -3,6 +3,7 @@
3 3
 from migen.fhdl.structure import *
4 4
 from migen.fhdl.structure import _Slice, _Assign
5 5
 from migen.fhdl.visit import NodeVisitor, NodeTransformer
  6
+from migen.fhdl.size import value_bits_sign
6 7
 
7 8
 def bitreverse(s):
8 9
 	length, signed = value_bits_sign(s)
7  migen/fhdl/verilog.py
@@ -4,6 +4,7 @@
4 4
 from migen.fhdl.structure import *
5 5
 from migen.fhdl.structure import _Operator, _Slice, _Assign
6 6
 from migen.fhdl.tools import *
  7
+from migen.fhdl.size import bits_for, flen
7 8
 from migen.fhdl.namer import Namespace, build_namespace
8 9
 
9 10
 def _printsig(ns, s):
@@ -11,8 +12,8 @@ def _printsig(ns, s):
11 12
 		n = "signed "
12 13
 	else:
13 14
 		n = ""
14  
-	if len(s) > 1:
15  
-		n += "[" + str(len(s)-1) + ":0] "
  15
+	if flen(s) > 1:
  16
+		n += "[" + str(flen(s)-1) + ":0] "
16 17
 	n += ns.get_name(s)
17 18
 	return n
18 19
 
@@ -63,7 +64,7 @@ def _printexpr(ns, node):
63 64
 	elif isinstance(node, _Slice):
64 65
 		# Verilog does not like us slicing non-array signals...
65 66
 		if isinstance(node.value, Signal) \
66  
-		  and len(node.value) == 1 \
  67
+		  and flen(node.value) == 1 \
67 68
 		  and node.start == 0 and node.stop == 1:
68 69
 			  return _printexpr(ns, node.value)
69 70
 
3  migen/flow/actor.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.genlib.misc import optree
4 3
 from migen.genlib.record import *
5 4
 
3  migen/flow/hooks.py
... ...
@@ -1,7 +1,6 @@
1 1
 from collections import defaultdict
2 2
 
3  
-from migen.fhdl.structure import *
4  
-from migen.fhdl.module import Module
  3
+from migen.fhdl.std import *
5 4
 from migen.flow.actor import *
6 5
 
7 6
 class EndpointSimHook(Module):
3  migen/flow/isd.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.bank.description import *
4 3
 from migen.flow.hooks import DFGHook
5 4
 
2  migen/flow/network.py
... ...
@@ -1,6 +1,6 @@
1 1
 from networkx import MultiDiGraph
2 2
 
3  
-from migen.fhdl.structure import *
  3
+from migen.fhdl.std import *
4 4
 from migen.genlib.misc import optree
5 5
 from migen.flow.actor import *
6 6
 from migen.flow import plumbing
3  migen/flow/plumbing.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.flow.actor import *
4 3
 from migen.genlib.record import *
5 4
 from migen.genlib.misc import optree
2  migen/genlib/buffers.py
... ...
@@ -1,4 +1,4 @@
1  
-from migen.fhdl.structure import *
  1
+from migen.fhdl.std import *
2 2
 
3 3
 class ReorderSlot:
4 4
 	def __init__(self, tag_width, data_width):
4  migen/genlib/cdc.py
... ...
@@ -1,5 +1,5 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
  2
+from migen.fhdl.size import value_bits_sign
3 3
 from migen.fhdl.specials import Special
4 4
 from migen.fhdl.tools import list_signals
5 5
 
2  migen/genlib/complex.py
... ...
@@ -1,4 +1,4 @@
1  
-from migen.fhdl.structure import *
  1
+from migen.fhdl.std import *
2 2
 
3 3
 class Complex:
4 4
 	def __init__(self, real, imag):
14  migen/genlib/divider.py
... ...
@@ -1,9 +1,7 @@
1  
-from migen.fhdl.structure import *
  1
+from migen.fhdl.std import *
2 2
 
3  
-class Divider:
  3
+class Divider(Module):
4 4
 	def __init__(self, w):
5  
-		self.w = w
6  
-		
7 5
 		self.start_i = Signal()
8 6
 		self.dividend_i = Signal(w)
9 7
 		self.divisor_i = Signal(w)
@@ -11,21 +9,20 @@ def __init__(self, w):
11 9
 		self.quotient_o = Signal(w)
12 10
 		self.remainder_o = Signal(w)
13 11
 	
14  
-	def get_fragment(self):
15  
-		w = self.w
  12
+		###
16 13
 		
17 14
 		qr = Signal(2*w)
18 15
 		counter = Signal(max=w+1)
19 16
 		divisor_r = Signal(w)
20 17
 		diff = Signal(w+1)
21 18
 		
22  
-		comb = [
  19
+		self.comb += [
23 20
 			self.quotient_o.eq(qr[:w]),
24 21
 			self.remainder_o.eq(qr[w:]),
25 22
 			self.ready_o.eq(counter == 0),
26 23
 			diff.eq(self.remainder_o - divisor_r)
27 24
 		]
28  
-		sync = [
  25
+		self.sync += [
29 26
 			If(self.start_i,
30 27
 				counter.eq(w),
31 28
 				qr.eq(self.dividend_i),
@@ -39,4 +36,3 @@ def get_fragment(self):
39 36
 					counter.eq(counter - 1)
40 37
 			)
41 38
 		]
42  
-		return Fragment(comb, sync)
6  migen/genlib/fifo.py
... ...
@@ -1,10 +1,8 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.specials import Memory
3  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
4 2
 from migen.genlib.cdc import NoRetiming, MultiReg, GrayCounter
5 3
 
6 4
 def _inc(signal, modulo):
7  
-	if modulo == 2**len(signal):
  5
+	if modulo == 2**flen(signal):
8 6
 		return signal.eq(signal + 1)
9 7
 	else:
10 8
 		return If(signal == (modulo - 1),
2  migen/genlib/fsm.py
... ...
@@ -1,4 +1,4 @@
1  
-from migen.fhdl.structure import *
  1
+from migen.fhdl.std import *
2 2
 
3 3
 class FSM:
4 4
 	def __init__(self, *states, delayed_enters=[]):
3  migen/genlib/ioo.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.specials import Memory
  1
+from migen.fhdl.std import *
3 2
 from migen.flow.actor import *
4 3
 from migen.flow.actor import _Endpoint
5 4
 from migen.flow.transactions import *
10  migen/genlib/misc.py
... ...
@@ -1,4 +1,4 @@
1  
-from migen.fhdl.structure import *
  1
+from migen.fhdl.std import *
2 2
 from migen.fhdl.structure import _Operator
3 3
 
4 4
 def optree(op, operands, lb=None, ub=None, default=None):
@@ -30,8 +30,8 @@ def split(v, *counts):
30 30
 
31 31
 def displacer(signal, shift, output, n=None, reverse=False):
32 32
 	if n is None:
33  
-		n = 2**len(shift)
34  
-	w = len(signal)
  33
+		n = 2**flen(shift)
  34
+	w = flen(signal)
35 35
 	if reverse:
36 36
 		r = reversed(range(n))
37 37
 	else:
@@ -41,8 +41,8 @@ def displacer(signal, shift, output, n=None, reverse=False):
41 41
 
42 42
 def chooser(signal, shift, output, n=None, reverse=False):
43 43
 	if n is None:
44  
-		n = 2**len(shift)
45  
-	w = len(output)
  44
+		n = 2**flen(shift)
  45
+	w = flen(output)
46 46
 	cases = {}
47 47
 	for i in range(n):
48 48
 		if reverse:
2  migen/genlib/record.py
... ...
@@ -1,4 +1,4 @@
1  
-from migen.fhdl.structure import *
  1
+from migen.fhdl.std import *
2 2
 from migen.fhdl.tracer import get_obj_var_name
3 3
 from migen.genlib.misc import optree
4 4
 
24  migen/genlib/roundrobin.py
... ...
@@ -1,23 +1,23 @@
1  
-from migen.fhdl.structure import *
  1
+from migen.fhdl.std import *
2 2
 
3 3
 (SP_WITHDRAW, SP_CE) = range(2)
4 4
 
5  
-class RoundRobin:
  5
+class RoundRobin(Module):
6 6
 	def __init__(self, n, switch_policy=SP_WITHDRAW):
7  
-		self.n = n
8  
-		self.request = Signal(self.n)
9  
-		self.grant = Signal(max=self.n)
  7
+		self.request = Signal(n)
  8
+		self.grant = Signal(max=n)
10 9
 		self.switch_policy = switch_policy
11 10
 		if self.switch_policy == SP_CE:
12 11
 			self.ce = Signal()
13 12
 	
14  
-	def get_fragment(self):
15  
-		if self.n > 1:
  13
+		###
  14
+
  15
+		if n > 1:
16 16
 			cases = {}
17  
-			for i in range(self.n):
  17
+			for i in range(n):
18 18
 				switch = []
19  
-				for j in reversed(range(i+1,i+self.n)):
20  
-					t = j % self.n
  19
+				for j in reversed(range(i+1,i+n)):
  20
+					t = j % n
21 21
 					switch = [
22 22
 						If(self.request[t],
23 23
 							self.grant.eq(t)
@@ -33,6 +33,6 @@ def get_fragment(self):
33 33
 			statement = Case(self.grant, cases)
34 34
 			if self.switch_policy == SP_CE:
35 35
 				statement = If(self.ce, statement)
36  
-			return Fragment(sync=[statement])
  36
+			self.sync += statement
37 37
 		else:
38  
-			return Fragment([self.grant.eq(0)])
  38
+			self.comb += self.grant.eq(0)
3  migen/pytholite/io.py
... ...
@@ -1,8 +1,7 @@
1 1
 import ast
2 2
 from itertools import zip_longest
3 3
 
4  
-from migen.fhdl.structure import *
5  
-from migen.fhdl.specials import Memory
  4
+from migen.fhdl.std import *
6 5
 from migen.flow.actor import Source, Sink
7 6
 from migen.flow.transactions import *
8 7
 from migen.bus import wishbone
3  migen/pytholite/reg.py
... ...
@@ -1,7 +1,6 @@
1 1
 from operator import itemgetter
2 2
 
3  
-from migen.fhdl.structure import *
4  
-from migen.fhdl.module import Module
  3
+from migen.fhdl.std import *
5 4
 from migen.fhdl import visit as fhdl
6 5
 
7 6
 class AbstractLoad:
10  migen/sim/generic.py
... ...
@@ -1,8 +1,4 @@
1  
-# Copyright (C) 2012 Vermeer Manufacturing Co.
2  
-# License: GPLv3 with additional permissions (see README).
3  
-
4  
-from migen.fhdl.structure import *
5  
-from migen.fhdl.specials import Memory
  1
+from migen.fhdl.std import *
6 2
 from migen.fhdl import verilog
7 3
 from migen.sim.ipc import *
8 4
 from migen.sim import icarus
@@ -132,7 +128,7 @@ def rd(self, item, index=0):
132 128
 			nbits = item.width
133 129
 		else:
134 130
 			signed = item.signed
135  
-			nbits = len(item)
  131
+			nbits = flen(item)
136 132
 		value = reply.value & (2**nbits - 1)
137 133
 		if signed and (value & 2**(nbits - 1)):
138 134
 			value -= 2**nbits
@@ -145,7 +141,7 @@ def wr(self, item, value, index=0):
145 141
 		if isinstance(item, Memory):
146 142
 			nbits = item.width
147 143
 		else:
148  
-			nbits = len(item)
  144
+			nbits = flen(item)
149 145
 		if value < 0:
150 146
 			value += 2**nbits
151 147
 		assert(value >= 0 and value < 2**nbits)

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