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fhdl: remove _StatementList

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1 parent a55fee7 commit 7f47a2568a414139524baca2edd0961d92307d44 @sbourdeauducq sbourdeauducq committed Jul 13, 2012
Showing with 34 additions and 46 deletions.
  1. +15 −26 migen/fhdl/structure.py
  2. +11 −12 migen/fhdl/tools.py
  3. +8 −8 migen/fhdl/verilog.py
View
@@ -174,54 +174,43 @@ def __init__(self, l, r):
self.l = l
self.r = _cst(r)
-class _StatementList:
- def __init__(self, l=None):
- if l is None: l = []
- self.l = l
-
class If:
def __init__(self, cond, *t):
self.cond = cond
- self.t = _StatementList(t)
- self.f = _StatementList()
+ self.t = list(t)
+ self.f = []
def Else(self, *f):
- _insert_else(self, _StatementList(f))
+ _insert_else(self, list(f))
return self
def Elif(self, cond, *t):
- _insert_else(self, _StatementList([If(cond, *t)]))
+ _insert_else(self, [If(cond, *t)])
return self
def _insert_else(obj, clause):
o = obj
- while o.f.l:
- assert(len(o.f.l) == 1)
- assert(isinstance(o.f.l[0], If))
- o = o.f.l[0]
+ while o.f:
+ assert(len(o.f) == 1)
+ assert(isinstance(o.f[0], If))
+ o = o.f[0]
o.f = clause
-def _sl(x):
- if isinstance(x, list):
- return _StatementList(x)
- else:
- return x
-
class Default:
pass
class Case:
def __init__(self, test, *cases):
self.test = test
- self.cases = [(c[0], _StatementList(c[1:])) for c in cases if not isinstance(c[0], Default)]
+ self.cases = [(c[0], list(c[1:])) for c in cases if not isinstance(c[0], Default)]
self.default = None
for c in cases:
if isinstance(c[0], Default):
if self.default is not None:
raise ValueError
- self.default = _StatementList(c[1:])
+ self.default = list(c[1:])
if self.default is None:
- self.default = _StatementList()
+ self.default = []
# arrays
@@ -301,15 +290,15 @@ def __init__(self, comb=None, sync=None, instances=None, memories=None, sim=None
if instances is None: instances = []
if memories is None: memories = []
if sim is None: sim = []
- self.comb = _sl(comb)
- self.sync = _sl(sync)
+ self.comb = comb
+ self.sync = sync
self.instances = instances
self.memories = memories
self.sim = sim
def __add__(self, other):
- return Fragment(self.comb.l + other.comb.l,
- self.sync.l + other.sync.l,
+ return Fragment(self.comb + other.comb,
+ self.sync + other.sync,
self.instances + other.instances,
self.memories + other.memories,
self.sim + other.sim)
View
@@ -1,7 +1,7 @@
from copy import copy
from migen.fhdl.structure import *
-from migen.fhdl.structure import _Operator, _Slice, _Assign, _StatementList, _ArrayProxy
+from migen.fhdl.structure import _Operator, _Slice, _Assign, _ArrayProxy
def list_signals(node):
if node is None:
@@ -22,8 +22,8 @@ def list_signals(node):
return list_signals(node.v)
elif isinstance(node, _Assign):
return list_signals(node.l) | list_signals(node.r)
- elif isinstance(node, _StatementList):
- l = list(map(list_signals, node.l))
+ elif isinstance(node, list):
+ l = list(map(list_signals, node))
return set().union(*l)
elif isinstance(node, If):
return list_signals(node.cond) | list_signals(node.t) | list_signals(node.f)
@@ -47,8 +47,8 @@ def list_targets(node):
return set().union(*l)
elif isinstance(node, _Assign):
return list_targets(node.l)
- elif isinstance(node, _StatementList):
- l = list(map(list_targets, node.l))
+ elif isinstance(node, list):
+ l = list(map(list_targets, node))
return set().union(*l)
elif isinstance(node, If):
return list_targets(node.t) | list_targets(node.f)
@@ -62,7 +62,7 @@ def list_targets(node):
def group_by_targets(sl):
groups = []
- for statement in sl.l:
+ for statement in sl:
targets = list_targets(statement)
processed = False
for g in groups:
@@ -124,7 +124,7 @@ def is_variable(node):
def insert_reset(rst, sl):
targets = list_targets(sl)
resetcode = [t.eq(t.reset) for t in targets]
- return If(rst, *resetcode).Else(*sl.l)
+ return If(rst, *resetcode).Else(*sl)
def value_bv(v):
if isinstance(v, Constant):
@@ -215,10 +215,9 @@ def _lower_arrays_assign(l, r):
return _Assign(l, r), extra_comb
def _lower_arrays_sl(sl):
- result = _StatementList()
- rs = result.l
+ rs = []
extra_comb = []
- for statement in sl.l:
+ for statement in sl:
if isinstance(statement, _Assign):
r, e = _lower_arrays_value(statement.r)
extra_comb += e
@@ -250,11 +249,11 @@ def _lower_arrays_sl(sl):
rs.append(c)
elif statement is not None:
raise TypeError
- return result, extra_comb
+ return rs, extra_comb
def lower_arrays(f):
f = copy(f)
f.comb, ec1 = _lower_arrays_sl(f.comb)
f.sync, ec2 = _lower_arrays_sl(f.sync)
- f.comb.l += ec1 + ec2
+ f.comb += ec1 + ec2
return f
View
@@ -1,7 +1,7 @@
from functools import partial
from migen.fhdl.structure import *
-from migen.fhdl.structure import _Operator, _Slice, _Assign, _StatementList
+from migen.fhdl.structure import _Operator, _Slice, _Assign
from migen.fhdl.tools import *
from migen.fhdl.namer import Namespace, build_namespace
from migen.fhdl import verilog_mem_behavioral
@@ -69,12 +69,12 @@ def _printnode(ns, at, level, node):
else:
assignment = " <= "
return "\t"*level + _printexpr(ns, node.l) + assignment + _printexpr(ns, node.r) + ";\n"
- elif isinstance(node, _StatementList):
- return "".join(list(map(partial(_printnode, ns, at, level), node.l)))
+ elif isinstance(node, list):
+ return "".join(list(map(partial(_printnode, ns, at, level), node)))
elif isinstance(node, If):
r = "\t"*level + "if (" + _printexpr(ns, node.cond) + ") begin\n"
r += _printnode(ns, at, level + 1, node.t)
- if node.f.l:
+ if node.f:
r += "\t"*level + "end else begin\n"
r += _printnode(ns, at, level + 1, node.f)
r += "\t"*level + "end\n"
@@ -85,7 +85,7 @@ def _printnode(ns, at, level, node):
r += "\t"*(level + 1) + _printexpr(ns, case[0]) + ": begin\n"
r += _printnode(ns, at, level + 2, case[1])
r += "\t"*(level + 1) + "end\n"
- if node.default.l:
+ if node.default:
r += "\t"*(level + 1) + "default: begin\n"
r += _printnode(ns, at, level + 2, node.default)
r += "\t"*(level + 1) + "end\n"
@@ -134,7 +134,7 @@ def _printheader(f, ios, name, ns):
def _printcomb(f, ns, display_run):
r = ""
- if f.comb.l:
+ if f.comb:
# Generate a dummy event to get the simulator
# to run the combinatorial process once at the beginning.
syn_off = "// synthesis translate off\n"
@@ -161,7 +161,7 @@ def _printcomb(f, ns, display_run):
r += "\t$display(\"Running comb block #" + str(n) + "\");\n"
for t in g[0]:
r += "\t" + ns.get_name(t) + " <= " + str(t.reset) + ";\n"
- r += _printnode(ns, _AT_NONBLOCKING, 1, _StatementList(g[1]))
+ r += _printnode(ns, _AT_NONBLOCKING, 1, g[1])
r += syn_off
r += "\t" + ns.get_name(dummy_d) + " <= " + ns.get_name(dummy_s) + ";\n"
r += syn_on
@@ -171,7 +171,7 @@ def _printcomb(f, ns, display_run):
def _printsync(f, ns, clk, rst):
r = ""
- if f.sync.l:
+ if f.sync:
r += "always @(posedge " + ns.get_name(clk) + ") begin\n"
r += _printnode(ns, _AT_SIGNAL, 1, insert_reset(rst, f.sync))
r += "end\n\n"

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