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bus/asmibus: use implicit finalization

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commit 80970b203c436af87a2133e7b9ce927c23cb5df1 1 parent b042757
Sébastien Bourdeauducq authored March 11, 2013

Showing 1 changed file with 11 additions and 17 deletions. Show diff stats Hide diff stats

  1. 28  migen/bus/asmibus.py
28  migen/bus/asmibus.py
@@ -43,8 +43,9 @@ def __init__(self, aw, time):
43 43
 			]
44 44
 
45 45
 class Port(Module):
46  
-	def __init__(self, hub, nslots):
  46
+	def __init__(self, hub, base, nslots):
47 47
 		self.hub = hub
  48
+		self.base = base
48 49
 		self.submodules.slots = [Slot(self.hub.aw, self.hub.time) for i in range(nslots)]
49 50
 		
50 51
 		# request issuance
@@ -61,15 +62,11 @@ def __init__(self, hub, nslots):
61 62
 		self.dat_w = Signal(self.hub.dw)
62 63
 		self.dat_wm = Signal(self.hub.dw//8)
63 64
 
64  
-	def set_position(self, tagbits, base):
65  
-		self.tagbits = tagbits
66  
-		self.base = base
67  
-
68 65
 	def do_finalize(self):
69 66
 		nslots = len(self.slots)
70 67
 		if nslots > 1:
71 68
 			self.tag_issue = Signal(max=nslots)
72  
-		self.tag_call = Signal(self.tagbits)
  69
+		self.tag_call = Signal(self.hub.tagbits)
73 70
 
74 71
 		# allocate
75 72
 		for s in self.slots:
@@ -103,7 +100,10 @@ def __init__(self, aw, dw, time=0):
103 100
 		self.aw = aw
104 101
 		self.dw = dw
105 102
 		self.time = time
  103
+
106 104
 		self.ports = []
  105
+		self._next_base = 0
  106
+		self.tagbits = 0
107 107
 		
108 108
 		self.call = Signal()
109 109
 		# tag_call is created by do_finalize()
@@ -114,21 +114,15 @@ def __init__(self, aw, dw, time=0):
114 114
 	def get_port(self, nslots=1):
115 115
 		if self.finalized:
116 116
 			raise FinalizeError
117  
-		new_port = Port(self, nslots)
  117
+		new_port = Port(self, self._next_base, nslots)
  118
+		self._next_base += nslots
  119
+		self.tagbits = bits_for(self._next_base-1)
118 120
 		self.ports.append(new_port)
  121
+		self.submodules += new_port
119 122
 		return new_port
120 123
 	
121 124
 	def do_finalize(self):
122  
-		nslots = sum([len(port.slots) for port in self.ports])
123  
-		tagbits = bits_for(nslots-1)
124  
-		base = 0
125  
-		for port in self.ports:
126  
-			port.set_position(tagbits, base)
127  
-			port.finalize()
128  
-			base += len(port.slots)
129  
-		self.submodules += self.ports
130  
-		self.tag_call = Signal(tagbits)
131  
-		
  125
+		self.tag_call = Signal(self.tagbits)
132 126
 		for port in self.ports:
133 127
 			self.comb += [
134 128
 				port.call.eq(self.call),

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