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bus: Wishbone -> LASMI bridge (untested)

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commit 932bfa7e759b2a9f637795e0d0f8f486149853b6 1 parent 9f560cb
Sébastien Bourdeauducq authored June 10, 2013

Showing 1 changed file with 125 additions and 0 deletions. Show diff stats Hide diff stats

  1. 125  migen/bus/wishbone2lasmi.py
125  migen/bus/wishbone2lasmi.py
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+from migen.fhdl.std import *
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+from migen.bus import wishbone
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+from migen.genlib.fsm import FSM
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+from migen.genlib.misc import split, displacer, chooser
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+from migen.genlib.record import Record, layout_len
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+
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+# cachesize (in 32-bit words) is the size of the data store, must be a power of 2
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+class WB2LASMI(Module):
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+	def __init__(self, cachesize, lasmim):
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+		self.wishbone = wishbone.Interface()
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+
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+		###
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+
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+		if lasmim.dw <= 32:
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+			raise ValueError("LASMI data width must be strictly larger than 32")
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+		if (lasmim.dw % 32) != 0:
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+			raise ValueError("LASMI data width must be a multiple of 32")
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+
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+		# Split address:
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+		# TAG | LINE NUMBER | LINE OFFSET
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+		offsetbits = log2_int(lasmim.dw//32)
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+		addressbits = lasmim.aw + offsetbits
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+		linebits = log2_int(self.cachesize) - offsetbits
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+		tagbits = addressbits - linebits
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+		adr_offset, adr_line, adr_tag = split(self.wishbone.adr, offsetbits, linebits, tagbits)
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+		
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+		# Data memory
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+		data_mem = Memory(lasmim.dw, 2**linebits)
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+		data_port = data_mem.get_port(write_capable=True, we_granularity=8)
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+		self.specials += data_mem, data_port
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+		
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+		write_from_lasmi = Signal()
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+		write_to_lasmi = Signal()
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+		adr_offset_r = Signal(offsetbits)
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+		self.comb += [
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+			data_port.adr.eq(adr_line),
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+			If(write_from_lasmi,
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+				data_port.dat_w.eq(lasmim.dat_r),
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+				data_port.we.eq(Replicate(1, lasmim.dw//8))
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+			).Else(
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+				data_port.dat_w.eq(Replicate(self.wishbone.dat_w, lasmim.dw//32)),
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+				If(self.wishbone.cyc & self.wishbone.stb & self.wishbone.we & self.wishbone.ack,
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+					displacer(self.wishbone.sel, adr_offset, data_port.we, 2**offsetbits, reverse=True)
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+				)
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+			),
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+			If(write_to_lasmi, 
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+				lasmim.dat_w.eq(data_port.dat_r),
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+				lasmim.dat_we.eq(2**(lasmim.dw//8)-1)
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+			),
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+			chooser(data_port.dat_r, adr_offset_r, self.wishbone.dat_r, reverse=True)
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+		]
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+		self.sync += adr_offset_r.eq(adr_offset)
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+		
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+		# Tag memory
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+		tag_layout = [("tag", tagbits), ("dirty", 1)]
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+		tag_mem = Memory(layout_len(tag_layout), 2**linebits)
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+		tag_port = tag_mem.get_port(write_capable=True)
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+		self.specials += tag_mem, tag_port
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+		tag_do = Record(tag_layout)
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+		tag_di = Record(tag_layout)
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+		self.comb += [
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+			tag_do.raw_bits().eq(tag_port.dat_r),
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+			tag_port.dat_w.eq(tag_di.raw_bits())
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+		]
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+			
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+		self.comb += [
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+			tag_port.adr.eq(adr_line),
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+			tag_di.tag.eq(adr_tag),
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+			lasmim.adr.eq(Cat(adr_line, tag_do.tag))
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+		]
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+		
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+		# Control FSM
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+		assert(lasmim.write_latency >= 1 and lasmim.read_latency >= 1)
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+		fsm = FSM("IDLE", "TEST_HIT",
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+			"EVICT_REQUEST", "EVICT_DATA",
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+			"REFILL_WRTAG", "REFILL_REQUEST", "REFILL_DATA",
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+			delayed_enters=[
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+				("EVICT_DATAD", "EVICT_DATA", lasmim.write_latency-1),
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+				("REFILL_DATAD", "REFILL_DATA", lasmim.read_latency-1)
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+			])
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+		self.submodules += fsm
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+		
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+		fsm.act(fsm.IDLE,
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+			If(self.wishbone.cyc & self.wishbone.stb, fsm.next_state(fsm.TEST_HIT))
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+		)
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+		fsm.act(fsm.TEST_HIT,
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+			If(tag_do.tag == adr_tag,
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+				self.wishbone.ack.eq(1),
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+				If(self.wishbone.we,
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+					tag_di.dirty.eq(1),
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+					tag_port.we.eq(1)
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+				),
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+				fsm.next_state(fsm.IDLE)
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+			).Else(
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+				If(tag_do.dirty,
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+					fsm.next_state(fsm.EVICT_ISSUE)
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+				).Else(
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+					fsm.next_state(fsm.REFILL_WRTAG)
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+				)
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+			)
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+		)
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+		
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+		fsm.act(fsm.EVICT_REQUEST,
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+			lasmim.stb.eq(1),
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+			lasmim.we.eq(1),
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+			If(lasmim.ack, fsm.next_state(fsm.EVICT_DATAD))
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+		)
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+		fsm.act(fsm.EVICT_DATA,
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+			write_to_lasmi.eq(1),
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+			fsm.next_state(fsm.REFILL_WRTAG)
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+		)
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+		
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+		fsm.act(fsm.REFILL_WRTAG,
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+			# Write the tag first to set the LASMI address
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+			tag_port.we.eq(1),
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+			fsm.next_state(fsm.REFILL_REQUEST)
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+		)
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+		fsm.act(fsm.REFILL_REQUEST,
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+			lasmim.stb.eq(1),
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+			If(lasmim.ack, fsm.next_state(fsm.REFILL_DATAD))
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+		)
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+		fsm.act(fsm.REFILL_DATA,
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+			write_from_asmi.eq(1),
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+			fsm.next_state(fsm.TEST_HIT)
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+		)

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