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fhdl/verilog: properly connect instance inouts

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commit a1ad30faab428905349214643837a1deed861b20 1 parent ca7056b
@sbourdeauducq sbourdeauducq authored
Showing with 1 addition and 1 deletion.
  1. +1 −1  migen/fhdl/verilog.py
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2  migen/fhdl/verilog.py
@@ -198,7 +198,7 @@ def _printinstances(f, ns, clk, rst):
r += ns.get_name(x)
if x.parameters: r += " "
r += "(\n"
- ports = list(x.ins.items()) + list(x.outs.items())
+ ports = list(x.ins.items()) + list(x.outs.items()) + list(x.inouts.items())
if x.clkport:
ports.append((x.clkport, clk))
if x.rstport:
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