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genlib/cdc/MultiReg: output clock domain defaults to sys

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1 parent b38818e commit a94bf3b2c5f235ddb4e28b5e5ef0caa6c147f5fe @sbourdeauducq sbourdeauducq committed
Showing with 1 addition and 1 deletion.
  1. +1 −1 migen/genlib/
2 migen/genlib/
@@ -23,7 +23,7 @@ def get_fragment(self):
return Fragment(comb, {self.odomain: o_sync})
class MultiReg(Special):
- def __init__(self, i, o, odomain, n=2):
+ def __init__(self, i, o, odomain="sys", n=2):
self.i = i
self.o = o

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