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wishbone: base TargetModel class

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commit b7a84b37501ac3426af8fb843e278ccf73faa11b 1 parent ec501e7
@sbourdeauducq sbourdeauducq authored
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5 examples/dataflow_dma.py
@@ -9,16 +9,13 @@
from migen.sim.generic import Simulator
from migen.sim.icarus import Runner
-class MyModel:
+class MyModel(wishbone.TargetModel):
def __init__(self):
self.prng = Random(763627)
def read(self, address):
return address + 4
- def write(self, address, data, sel):
- pass
-
def can_ack(self, bus):
return self.prng.randrange(0, 2)
View
5 examples/wb_initiator.py
@@ -33,16 +33,13 @@ def my_generator():
yield None
# Our bus slave.
-class MyModel:
+class MyModel(wishbone.TargetModel):
def __init__(self):
self.prng = Random(763627)
def read(self, address):
return address + 4
- def write(self, address, data, sel):
- pass
-
def can_ack(self, bus):
return self.prng.randrange(0, 2)
View
16 migen/bus/wishbone.py
@@ -188,6 +188,16 @@ def do_simulation(self, s):
def get_fragment(self):
return Fragment(sim=[self.do_simulation])
+class TargetModel:
+ def read(self, address):
+ return 0
+
+ def write(self, address, data, sel):
+ pass
+
+ def can_ack(self, bus):
+ return True
+
class Target:
def __init__(self, model):
self.bus = Interface()
@@ -196,11 +206,7 @@ def __init__(self, model):
def do_simulation(self, s):
bus = Proxy(s, self.bus)
if not bus.ack:
- if hasattr(self.model, "can_ack"):
- can_ack = self.model.can_ack(bus)
- else:
- can_ack = True
- if can_ack and bus.cyc and bus.stb:
+ if self.model.can_ack(bus) and bus.cyc and bus.stb:
if bus.we:
self.model.write(bus.adr, bus.dat_w, bus.sel)
else:
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