Skip to content
This repository

HTTPS clone URL

Subversion checkout URL

You can clone with HTTPS or Subversion.

Download ZIP
Browse code

Make memory ports part of specials

This is needed to handle cases where a single memory has ports
in two different modules, and one of these modules is subject
to clock domain remapping. The clock domain of the port in that
module only must be remapped.
  • Loading branch information...
commit bac62a32a9a6537ff02d71a84a9948a7dee93dc0 1 parent 70ffe86
Sébastien Bourdeauducq authored May 28, 2013
1  examples/basic/memory.py
@@ -6,6 +6,7 @@ def __init__(self):
6 6
 		self.specials.mem = Memory(32, 100, init=[5, 18, 32])
7 7
 		p1 = self.mem.get_port(write_capable=True, we_granularity=8)
8 8
 		p2 = self.mem.get_port(has_re=True, clock_domain="rd")
  9
+		self.specials += p1, p2
9 10
 		self.ios = {p1.adr, p1.dat_r, p1.we, p1.dat_w,
10 11
 			p2.adr, p2.dat_r, p2.re}
11 12
 
1  migen/actorlib/spi.py
@@ -92,6 +92,7 @@ def __init__(self, layout, depth=1024):
92 92
 		self.specials += mem
93 93
 		wp = mem.get_port(write_capable=True)
94 94
 		rp = mem.get_port()
  95
+		self.specials += wp, rp
95 96
 		
96 97
 		self.comb += [
97 98
 			self.busy.eq(0),
2  migen/bus/csr.py
@@ -80,9 +80,9 @@ def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
80 80
 	
81 81
 		###
82 82
 
83  
-		self.specials += mem
84 83
 		port = mem.get_port(write_capable=not read_only,
85 84
 			we_granularity=data_width if not read_only and word_bits else 0)
  85
+		self.specials += mem, port
86 86
 		
87 87
 		sel = Signal()
88 88
 		sel_r = Signal()
2  migen/bus/wishbone.py
@@ -200,8 +200,8 @@ def __init__(self, mem_or_size, read_only=None, init=None, bus=None):
200 200
 		###
201 201
 	
202 202
 		# memory
203  
-		self.specials += mem
204 203
 		port = mem.get_port(write_capable=not read_only, we_granularity=8)
  204
+		self.specials += mem, port
205 205
 		# generate write enable signal
206 206
 		if not read_only:
207 207
 			self.comb += [port.we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
2  migen/bus/wishbone2asmi.py
@@ -135,5 +135,5 @@ def get_fragment(self):
135 135
 			fsm.next_state(fsm.TEST_HIT)
136 136
 		)
137 137
 		
138  
-		return Fragment(comb, sync, specials={data_mem, tag_mem}) \
  138
+		return Fragment(comb, sync, specials={data_mem, tag_mem, data_port, tag_port}) \
139 139
 			+ fsm.get_fragment()
28  migen/fhdl/specials.py
@@ -150,10 +150,11 @@ def emit_verilog(instance, ns):
150 150
 
151 151
 (READ_FIRST, WRITE_FIRST, NO_CHANGE) = range(3)
152 152
 
153  
-class _MemoryPort:
  153
+class _MemoryPort(Special):
154 154
 	def __init__(self, adr, dat_r, we=None, dat_w=None,
155 155
 	  async_read=False, re=None, we_granularity=0, mode=WRITE_FIRST,
156 156
 	  clock_domain="sys"):
  157
+		Special.__init__(self)
157 158
 		self.adr = adr
158 159
 		self.dat_r = dat_r
159 160
 		self.we = we
@@ -164,6 +165,20 @@ def __init__(self, adr, dat_r, we=None, dat_w=None,
164 165
 		self.mode = mode
165 166
 		self.clock = ClockSignal(clock_domain)
166 167
 
  168
+	def iter_expressions(self):
  169
+		for attr, target_context in [
  170
+		  ("adr", SPECIAL_INPUT),
  171
+		  ("we", SPECIAL_INPUT),
  172
+		  ("dat_w", SPECIAL_INPUT),
  173
+		  ("re", SPECIAL_INPUT),
  174
+		  ("dat_r", SPECIAL_OUTPUT),
  175
+		  ("clock", SPECIAL_INPUT)]:
  176
+			yield self, attr, target_context
  177
+
  178
+	@staticmethod
  179
+	def emit_verilog(port, ns):
  180
+		return "" # done by parent Memory object
  181
+
167 182
 class Memory(Special):
168 183
 	def __init__(self, width, depth, init=None, name=None):
169 184
 		Special.__init__(self)
@@ -199,17 +214,6 @@ def get_port(self, write_capable=False, async_read=False,
199 214
 		self.ports.append(mp)
200 215
 		return mp
201 216
 
202  
-	def iter_expressions(self):
203  
-		for p in self.ports:
204  
-			for attr, target_context in [
205  
-			  ("adr", SPECIAL_INPUT),
206  
-			  ("we", SPECIAL_INPUT),
207  
-			  ("dat_w", SPECIAL_INPUT),
208  
-			  ("re", SPECIAL_INPUT),
209  
-			  ("dat_r", SPECIAL_OUTPUT),
210  
-			  ("clock", SPECIAL_INPUT)]:
211  
-				yield p, attr, target_context
212  
-
213 217
 	@staticmethod
214 218
 	def emit_verilog(memory, ns):
215 219
 		r = ""
4  migen/genlib/fifo.py
@@ -40,6 +40,7 @@ def __init__(self, width, depth):
40 40
 		self.specials += storage
41 41
 
42 42
 		wrport = storage.get_port(write_capable=True)
  43
+		self.specials += wrport
43 44
 		self.comb += [
44 45
 			wrport.adr.eq(produce),
45 46
 			wrport.dat_w.eq(self.din),
@@ -48,6 +49,7 @@ def __init__(self, width, depth):
48 49
 		self.sync += If(do_write, _inc(produce, depth))
49 50
 
50 51
 		rdport = storage.get_port(async_read=True)
  52
+		self.specials += rdport
51 53
 		self.comb += [
52 54
 			rdport.adr.eq(consume),
53 55
 			self.dout.eq(rdport.dat_r)
@@ -103,12 +105,14 @@ def __init__(self, width, depth):
103 105
 		storage = Memory(width, depth)
104 106
 		self.specials += storage
105 107
 		wrport = storage.get_port(write_capable=True, clock_domain="write")
  108
+		self.specials += wrport
106 109
 		self.comb += [
107 110
 			wrport.adr.eq(produce.q_binary[:-1]),
108 111
 			wrport.dat_w.eq(self.din),
109 112
 			wrport.we.eq(produce.ce)
110 113
 		]
111 114
 		rdport = storage.get_port(clock_domain="read")
  115
+		self.specials += rdport
112 116
 		self.comb += [
113 117
 			rdport.adr.eq(consume.q_binary[:-1]),
114 118
 			self.dout.eq(rdport.dat_r)
8  migen/pytholite/compiler.py
@@ -237,8 +237,12 @@ def do_finalize(self):
237 237
 		UnifiedIOObject.do_finalize(self)
238 238
 		if self.get_dataflow():
239 239
 			self.busy.reset = 1
240  
-		self.memory_ports = dict((mem, mem.get_port(write_capable=True, we_granularity=8))
241  
-			for mem in self.__dict__.values() if isinstance(mem, Memory))
  240
+		self.memory_ports = dict()
  241
+		for mem in self.__dict__.values():
  242
+			if isinstance(mem, Memory):
  243
+				port = mem.get_port(write_capable=True, we_granularity=8)
  244
+				self.specials += port
  245
+				self.memory_ports[mem] = port
242 246
 		self._compile()
243 247
 
244 248
 	def _compile(self):

0 notes on commit bac62a3

Please sign in to comment.
Something went wrong with that request. Please try again.