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genlib/fifo: support RecordP

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commit c0d2b5a78947814eeb9476fe7ca4c1e3d27e02f4 1 parent 018afe5
Sébastien Bourdeauducq authored October 21, 2013

Showing 1 changed file with 7 additions and 7 deletions. Show diff stats Hide diff stats

  1. 14  migen/genlib/fifo.py
14  migen/genlib/fifo.py
@@ -19,18 +19,18 @@ def __init__(self, width_or_layout, depth):
19 19
 		self.re = Signal()
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 		self.readable = Signal() # not empty
21 21
 
22  
-		if isinstance(width_or_layout, list):
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-			self.din = Record(width_or_layout)
24  
-			self.dout = Record(width_or_layout)
25  
-			self.din_bits = self.din.raw_bits()
26  
-			self.dout_bits = self.dout.raw_bits()
27  
-			self.width = layout_len(width_or_layout)
28  
-		else:
  22
+		if isinstance(width_or_layout, (int, tuple)):
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 			self.din = Signal(width_or_layout)
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 			self.dout = Signal(width_or_layout)
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 			self.din_bits = self.din
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 			self.dout_bits = self.dout
33 27
 			self.width = width_or_layout
  28
+		else:
  29
+			self.din = Record(width_or_layout)
  30
+			self.dout = Record(width_or_layout)
  31
+			self.din_bits = self.din.raw_bits()
  32
+			self.dout_bits = self.dout.raw_bits()
  33
+			self.width = layout_len(width_or_layout)
34 34
 
35 35
 class SyncFIFO(Module, _FIFOInterface):
36 36
 	def __init__(self, width_or_layout, depth):

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