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genlib/fifo: support RecordP

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commit c0d2b5a78947814eeb9476fe7ca4c1e3d27e02f4 1 parent 018afe5
Sébastien Bourdeauducq sbourdeauducq authored
Showing with 7 additions and 7 deletions.
  1. +7 −7 migen/genlib/fifo.py
14 migen/genlib/fifo.py
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@@ -19,18 +19,18 @@ def __init__(self, width_or_layout, depth):
self.re = Signal()
self.readable = Signal() # not empty
- if isinstance(width_or_layout, list):
- self.din = Record(width_or_layout)
- self.dout = Record(width_or_layout)
- self.din_bits = self.din.raw_bits()
- self.dout_bits = self.dout.raw_bits()
- self.width = layout_len(width_or_layout)
- else:
+ if isinstance(width_or_layout, (int, tuple)):
self.din = Signal(width_or_layout)
self.dout = Signal(width_or_layout)
self.din_bits = self.din
self.dout_bits = self.dout
self.width = width_or_layout
+ else:
+ self.din = Record(width_or_layout)
+ self.dout = Record(width_or_layout)
+ self.din_bits = self.din.raw_bits()
+ self.dout_bits = self.dout.raw_bits()
+ self.width = layout_len(width_or_layout)
class SyncFIFO(Module, _FIFOInterface):
def __init__(self, width_or_layout, depth):
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