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fhdl/verilog: insert reset before listing signals

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commit c10622f5e295ec69e7e687a6bc65db0cd8afbb96 1 parent d2cbc70
Sébastien Bourdeauducq authored February 27, 2013
2  migen/fhdl/tools.py
@@ -86,7 +86,7 @@ def is_variable(node):
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 def insert_reset(rst, sl):
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 	targets = list_targets(sl)
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 	resetcode = [t.eq(t.reset) for t in sorted(targets, key=lambda x: x.huid)]
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-	return If(rst, *resetcode).Else(*sl)
  89
+	return [If(rst, *resetcode).Else(*sl)]
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 def value_bits_sign(v):
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 	if isinstance(v, bool):
9  migen/fhdl/verilog.py
@@ -200,11 +200,17 @@ def _printcomb(f, ns, display_run):
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 	r += "\n"
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 	return r
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  203
+def _insert_resets(f, clock_domains):
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+	newsync = dict()
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+	for k, v in f.sync.items():
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+		newsync[k] = insert_reset(clock_domains[k].rst, v)
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+	f.sync = newsync
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+
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 def _printsync(f, ns, clock_domains):
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 	r = ""
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 	for k, v in sorted(f.sync.items(), key=itemgetter(0)):
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 		r += "always @(posedge " + ns.get_name(clock_domains[k].clk) + ") begin\n"
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-		r += _printnode(ns, _AT_SIGNAL, 1, insert_reset(clock_domains[k].rst, v))
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+		r += _printnode(ns, _AT_SIGNAL, 1, v)
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 		r += "end\n\n"
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 	return r
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@@ -267,6 +273,7 @@ def convert(f, ios=None, name="top",
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 	f = lower_arrays(f)
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 	fs, lowered_specials = _lower_specials(special_overrides, f.specials)
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 	f += fs
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+	_insert_resets(f, clock_domains)
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 	ns = build_namespace(list_signals(f) \
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 		| list_special_ios(f, True, True, True) \

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