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fhdl/verilog: insert reset before listing signals

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commit c10622f5e295ec69e7e687a6bc65db0cd8afbb96 1 parent d2cbc70
@sbourdeauducq sbourdeauducq authored
Showing with 9 additions and 2 deletions.
  1. +1 −1  migen/fhdl/tools.py
  2. +8 −1 migen/fhdl/verilog.py
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2  migen/fhdl/tools.py
@@ -86,7 +86,7 @@ def is_variable(node):
def insert_reset(rst, sl):
targets = list_targets(sl)
resetcode = [t.eq(t.reset) for t in sorted(targets, key=lambda x: x.huid)]
- return If(rst, *resetcode).Else(*sl)
+ return [If(rst, *resetcode).Else(*sl)]
def value_bits_sign(v):
if isinstance(v, bool):
View
9 migen/fhdl/verilog.py
@@ -200,11 +200,17 @@ def _printcomb(f, ns, display_run):
r += "\n"
return r
+def _insert_resets(f, clock_domains):
+ newsync = dict()
+ for k, v in f.sync.items():
+ newsync[k] = insert_reset(clock_domains[k].rst, v)
+ f.sync = newsync
+
def _printsync(f, ns, clock_domains):
r = ""
for k, v in sorted(f.sync.items(), key=itemgetter(0)):
r += "always @(posedge " + ns.get_name(clock_domains[k].clk) + ") begin\n"
- r += _printnode(ns, _AT_SIGNAL, 1, insert_reset(clock_domains[k].rst, v))
+ r += _printnode(ns, _AT_SIGNAL, 1, v)
r += "end\n\n"
return r
@@ -267,6 +273,7 @@ def convert(f, ios=None, name="top",
f = lower_arrays(f)
fs, lowered_specials = _lower_specials(special_overrides, f.specials)
f += fs
+ _insert_resets(f, clock_domains)
ns = build_namespace(list_signals(f) \
| list_special_ios(f, True, True, True) \

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