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fhdl: support forwarding of bidirectional signals from instance ports

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1 parent c08687b commit ca7056b07fb90b9424fa33918b5d701577e23be9 @sbourdeauducq sbourdeauducq committed Feb 16, 2012
Showing with 16 additions and 11 deletions.
  1. +3 −4 examples/lm32_inst.py
  2. +2 −1 migen/fhdl/structure.py
  3. +4 −2 migen/fhdl/tools.py
  4. +7 −4 migen/fhdl/verilog.py
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7 examples/lm32_inst.py
@@ -32,10 +32,9 @@ def __init__(self):
("D_ACK_I", BV(1)),
("D_ERR_I", BV(1)),
("D_RTY_I", BV(1))],
- [],
- "clk_i",
- "rst_i",
- "lm32")
+ clkport="clk_i",
+ rstport="rst_i",
+ name="lm32")
def get_fragment(self):
return Fragment(instances=[self.inst])
View
3 migen/fhdl/structure.py
@@ -209,7 +209,7 @@ def __init__(self, test, *cases):
#
class Instance:
- def __init__(self, of, outs=[], ins=[], parameters=[], clkport="", rstport="", name=""):
+ def __init__(self, of, outs=[], ins=[], inouts=[], parameters=[], clkport="", rstport="", name=""):
self.of = of
if name:
self.name_override = name
@@ -224,6 +224,7 @@ def process_io(x):
raise TypeError
self.outs = dict(map(process_io, outs))
self.ins = dict(map(process_io, ins))
+ self.inouts = dict(map(process_io, inouts))
self.parameters = parameters
self.clkport = clkport
self.rstport = rstport
View
6 migen/fhdl/tools.py
@@ -73,16 +73,18 @@ def group_by_targets(sl):
groups.append((targets, [statement]))
return groups
-def list_inst_ios(i, ins, outs):
+def list_inst_ios(i, ins, outs, inouts):
if isinstance(i, Fragment):
- return list_inst_ios(i.instances, ins, outs)
+ return list_inst_ios(i.instances, ins, outs, inouts)
else:
l = []
for x in i:
if ins:
l += x.ins.values()
if outs:
l += x.outs.values()
+ if inouts:
+ l += x.inouts.values()
return set(l)
def list_mem_ios(m, ins, outs):
View
11 migen/fhdl/verilog.py
@@ -103,8 +103,9 @@ def _list_comb_wires(f):
return r
def _printheader(f, ios, name, ns):
- sigs = list_signals(f) | list_inst_ios(f, True, True) | list_mem_ios(f, True, True)
- inst_mem_outs = list_inst_ios(f, False, True) | list_mem_ios(f, False, True)
+ sigs = list_signals(f) | list_inst_ios(f, True, True, True) | list_mem_ios(f, True, True)
+ inst_mem_outs = list_inst_ios(f, False, True, False) | list_mem_ios(f, False, True)
+ inouts = list_inst_ios(f, False, False, True)
targets = list_targets(f) | inst_mem_outs
wires = _list_comb_wires(f) | inst_mem_outs
r = "module " + name + "(\n"
@@ -113,7 +114,9 @@ def _printheader(f, ios, name, ns):
if not firstp:
r += ",\n"
firstp = False
- if sig in targets:
+ if sig in inouts:
+ r += "\tinout " + _printsig(ns, sig)
+ elif sig in targets:
if sig in wires:
r += "\toutput " + _printsig(ns, sig)
else:
@@ -230,7 +233,7 @@ def convert(f, ios=set(), name="top",
ios |= f.pads
ns = build_namespace(list_signals(f) \
- | list_inst_ios(f, True, True) \
+ | list_inst_ios(f, True, True, True) \
| list_mem_ios(f, True, True) \
| ios)

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