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genlib/misc: fix import

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1 parent ebbd5eb commit cebfe787db78d61a4e77be1c9fa696ae590db4f3 @sbourdeauducq sbourdeauducq committed
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  1. +1 −0 migen/genlib/
1 migen/genlib/
@@ -1,4 +1,5 @@
from migen.fhdl.std import *
+from import value_bits_sign
from migen.fhdl.structure import _Operator
def bitreverse(s):

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