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sayma_amc2: add ddrXX_clk

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sbourdeauducq committed Feb 27, 2019
1 parent 25646d4 commit d482b93572f35de0b9f6d1106a691ddfa3a4e8e5
Showing with 8 additions and 4 deletions.
  1. +8 −4 migen/build/platforms/sinara/sayma_amc2.py
@@ -307,13 +307,17 @@
IOStandard("LVDS"), Misc("DIFF_TERM_ADV=TERM_100")
),

# has 100R external termination resistor
("sysclk1_300", 0,
# CDR clock, named ddr* as they are used for SDRAM testing with Xilinx MIG
("ddr64_clk", 0,
Subsignal("p", Pins("AK17")),
Subsignal("n", Pins("AK16")),
IOStandard("DIFF_SSTL15_DCI")
),
("ddr32_clk", 0,
Subsignal("p", Pins("F18")),
Subsignal("n", Pins("F17")),
IOStandard("DIFF_SSTL15_DCI"), Misc("OUTPUT_IMPEDANCE=RDRV_40_40")
IOStandard("DIFF_SSTL15_DCI")
),

]

# differences with Sayma v1: CLK1_M2C, DP0_M2C, GBTCLK0_M2C, LA08

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