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bank/csrgen: fix RE generation

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1 parent 55a265d commit d8d4e81b6e0624cb7055dbb147a967f5975f294b @sbourdeauducq sbourdeauducq committed Feb 18, 2012
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  1. +1 −0 migen/bank/csrgen.py
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@@ -27,6 +27,7 @@ def get_fragment(self):
self.interface.we & \
(self.interface.adr[:nbits] == Constant(i, BV(nbits)))))
elif isinstance(reg, RegisterFields):
+ sync.append(reg.re.eq(0))
bwra = [Constant(i, BV(nbits))]
offset = 0
for field in reg.fields:

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