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Support for resetless clock domains

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commit f599fe4ade7e9333837abbe7aa2ceda802593981 1 parent ceb0a99
EnjoyDigital authored April 23, 2013 sbourdeauducq committed April 23, 2013
2  examples/basic/local_cd.py
@@ -6,7 +6,7 @@
6 6
 class CDM(Module):
7 7
 	def __init__(self):
8 8
 		self.submodules.divider = Divider(5)
9  
-		self.clock_domains.cd_sys = ClockDomain()
  9
+		self.clock_domains.cd_sys = ClockDomain(reset_less=True)
10 10
 
11 11
 class MultiMod(Module):
12 12
 	def __init__(self):
10  migen/fhdl/structure.py
@@ -246,19 +246,23 @@ def __getitem__(self, key):
246 246
 			return list.__getitem__(self, key)
247 247
 
248 248
 class ClockDomain:
249  
-	def __init__(self, name=None):
  249
+	def __init__(self, name=None, reset_less=False):
250 250
 		self.name = tracer.get_obj_var_name(name)
251 251
 		if self.name is None:
252 252
 			raise ValueError("Cannot extract clock domain name from code, need to specify.")
253 253
 		if len(self.name) > 3 and self.name[:3] == "cd_":
254 254
 			self.name = self.name[3:]
255 255
 		self.clk = Signal(name_override=self.name + "_clk")
256  
-		self.rst = Signal(name_override=self.name + "_rst")
  256
+		if reset_less:
  257
+			self.rst = None
  258
+		else:
  259
+			self.rst = Signal(name_override=self.name + "_rst")
257 260
 
258 261
 	def rename(self, new_name):
259 262
 		self.name = new_name
260 263
 		self.clk.name_override = new_name + "_clk"
261  
-		self.rst.name_override = new_name + "_rst"
  264
+		if self.rst is not None:
  265
+			self.rst.name_override = new_name + "_rst"
262 266
 
263 267
 class _ClockDomainList(list):
264 268
 	def __getitem__(self, key):
8  migen/fhdl/tools.py
@@ -112,10 +112,12 @@ def is_variable(node):
112 112
 	else:
113 113
 		raise TypeError
114 114
 
115  
-def insert_reset(rst, sl):
  115
+def generate_reset(rst, sl):
116 116
 	targets = list_targets(sl)
117  
-	resetcode = [t.eq(t.reset) for t in sorted(targets, key=lambda x: x.huid)]
118  
-	return [If(rst, *resetcode).Else(*sl)]
  117
+	return [t.eq(t.reset) for t in sorted(targets, key=lambda x: x.huid)]
  118
+
  119
+def insert_reset(rst, sl):
  120
+	return [If(rst, *generate_reset(rst, sl)).Else(*sl)]
119 121
 
120 122
 # Basics are FHDL structure elements that back-ends are not required to support
121 123
 # but can be expressed in terms of other elements (lowered) before conversion.
9  migen/fhdl/verilog.py
@@ -203,12 +203,19 @@ def _printcomb(f, ns, display_run):
203 203
 def _insert_resets(f):
204 204
 	newsync = dict()
205 205
 	for k, v in f.sync.items():
206  
-		newsync[k] = insert_reset(ResetSignal(k), v)
  206
+		if f.clock_domains[k].rst is not None:
  207
+			newsync[k] = insert_reset(ResetSignal(k), v)
  208
+		else:
  209
+			newsync[k] = v
207 210
 	f.sync = newsync
208 211
 
209 212
 def _printsync(f, ns):
210 213
 	r = ""
211 214
 	for k, v in sorted(f.sync.items(), key=itemgetter(0)):
  215
+		if f.clock_domains[k].rst is None:
  216
+			r += "initial begin\n"
  217
+			r += _printnode(ns, _AT_SIGNAL, 1, generate_reset(ResetSignal(k), v))
  218
+			r += "end\n\n"
212 219
 		r += "always @(posedge " + ns.get_name(f.clock_domains[k].clk) + ") begin\n"
213 220
 		r += _printnode(ns, _AT_SIGNAL, 1, v)
214 221
 		r += "end\n\n"

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