Commits on Mar 12, 2018
Commits on Mar 9, 2018
  1. ku: fix IDDRE1 clocking

    sbourdeauducq committed Mar 9, 2018
    Prevents warnings (and more?) about CB being driven without a clock buffer.
Commits on Mar 7, 2018
Commits on Mar 5, 2018
  1. kasli: merge v1.0 and v1.1

    jordens committed Mar 5, 2018
  2. kasli_v1_1: add platform

    jordens committed Mar 5, 2018
Commits on Mar 2, 2018
  1. sayma_amc: take bitstream options from artiq, speed up load

    jordens committed Mar 2, 2018
    * 33 MHz CCLK
    * QSPI
    * compress
    * CFGBVS
Commits on Feb 27, 2018
  1. fhdl/verilog: list available clock domains in case of unresolved cloc…

    enjoy-digital committed Feb 27, 2018
    …k domain
    Migen automatically renames some clock domains (for example in the case of
    multiple modules defining a clock domain with the same name). When designing,
    we need in some cases to know the final name of the clock domain and displaying
    the list of avalaible clock domains helps figuring out what it is.
    We are using Exception instead of KeyError since KeyError is not able to display
    on multiple lines.
Commits on Feb 26, 2018
  1. vivado: remove post-synth and post-place checkpoints

    jordens committed Feb 26, 2018
    They are pretty big and post-route is usually interesting enough.
    People can also use post-route to add their own checkpoints.
Commits on Feb 25, 2018
  1. sim: more verbose exec/eval request ValueError

    jordens committed Feb 25, 2018
    also remove some whitespace
Commits on Feb 23, 2018
  1. sayma_rtm: pulldown HMC830/7043 cs

    jordens committed Feb 23, 2018
    * build an easy way for toggling cs to determine HMC830 SPI mode
    * no miso contention as HMC7043 is three-wire
  2. sayma: boost RGMII signals

    sbourdeauducq committed Feb 23, 2018
    Improves TX data eye from 0.5ns to 1.5ns.
Commits on Feb 19, 2018
  1. vivado: clock contraints: use groups, string properties

    jordens committed Feb 19, 2018
    * Clock groups to designate asynchronous clocks is the recommended
    way (ug903).
    * This now includes generated clocks (!). And clock groups are
    * Don't bother creating boolean properties. The design checkpoints don't
    have them which makes using the latter very hard. String properties are
    allowed automatically and work fine also in checkpoints.
    * Use pins to constrain the AsyncResetSynchronizers more precisely.
Commits on Feb 17, 2018
  1. migen/build/altera/ prevent conversion to RBF when no SOF …

    psurply authored and sbourdeauducq committed Feb 17, 2018
    …is generated (#100)
    When targeting CPLD devices, Quartus generates the bitstream as a POF
    file instead of SOF. It is not necessary to convert it to RBF bitstream
    format in that case.
    Signed-off-by: Pierre Surply <>
Commits on Feb 13, 2018
Commits on Jan 26, 2018
Commits on Jan 23, 2018
  1. vivado: only search for tagged objects at the top

    jordens committed Jan 23, 2018
    Don't descend the hierarchy into non-migen or external verilog/vhdl entities.
Commits on Jan 22, 2018
  1. xilinx: find false path inputs using pins

    jordens committed Jan 22, 2018
    * more robust than attaching custom attributes to nets which then
    seem to disappear
    * less custom attirbutes, more straight forward
  2. cdc: style

    jordens committed Jan 22, 2018
Commits on Jan 17, 2018
Commits on Jan 16, 2018