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Commits on May 26, 2017
Commits on May 8, 2017
Commits on Apr 25, 2017
  1. genlib/cdc: add Gearbox

    enjoy-digital committed Apr 25, 2017
  2. genlib/misc: add BitSlip

    ultrascale ISERDESE3 do not have integrated bitslip so we need one and that's probably better since Xilinx bitslip implementation is always obscure...
    We could also use it for Kintex7 and Spartan6 ddr phys.
    enjoy-digital committed Apr 25, 2017
  3. build/lattice/programmer: provide xcf_template on init (template is n…

    …ot generic enough to be in migen)
    enjoy-digital committed Apr 25, 2017
Commits on Apr 12, 2017
  1. Implement __contains__() method for _ClockDomainList class

    Fixes #66 issue which resulted in creation of redundant
    clock domains
    rohitk-singh committed with sbourdeauducq Apr 11, 2017
Commits on Apr 1, 2017
Commits on Mar 27, 2017
  1. doc: Fix tag link.

    mithro committed with sbourdeauducq Mar 27, 2017
  2. doc: Fixing the version info.

    mithro committed with sbourdeauducq Mar 27, 2017
Commits on Mar 11, 2017
  1. sinara: fix fpga id string

    sbourdeauducq committed Mar 11, 2017
  2. fix permissions

    sbourdeauducq committed Mar 11, 2017
Commits on Feb 20, 2017
  1. fix/update copyright info

    sbourdeauducq committed Feb 20, 2017
Commits on Feb 10, 2017
Commits on Jan 27, 2017
Commits on Jan 25, 2017
Commits on Dec 18, 2016
Commits on Dec 12, 2016
Commits on Nov 20, 2016
  1. Unbreak 51c23b8.

    whitequark committed Nov 20, 2016
  2. fhdl.structure: reject signal names that aren't valid Python identifi…

    …ers.
    
    Such signal names are unergonomic to use and will cause problems
    downstream, such as in fhdl.verilog.
    whitequark committed Nov 20, 2016