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  • 2 commits
  • 3 files changed
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  • 1 contributor
View
2  examples/simple_gpio.py
@@ -18,5 +18,5 @@
f = bank.get_fragment() + inf
oreg.field.r.name_override = "gpio_out"
i = bank.interface
-v = verilog.convert(f, {i.d_o, oreg.field.r, i.a_i, i.we_i, i.d_i, gpio_in})
+v = verilog.convert(f, {i.dat_r, oreg.field.r, i.adr, i.we, i.dat_w, gpio_in})
print(v)
View
26 migen/bank/csrgen.py
@@ -6,14 +6,14 @@ class Bank:
def __init__(self, description, address=0):
self.description = description
self.address = address
- self.interface = Slave()
+ self.interface = Interface()
def get_fragment(self):
comb = []
sync = []
sel = Signal()
- comb.append(sel.eq(self.interface.adr_i[9:] == Constant(self.address, BV(5))))
+ comb.append(sel.eq(self.interface.adr[9:] == Constant(self.address, BV(5))))
desc_exp = expand_description(self.description, 8)
nbits = bits_for(len(desc_exp)-1)
@@ -22,29 +22,29 @@ def get_fragment(self):
bwcases = []
for i, reg in enumerate(desc_exp):
if isinstance(reg, RegisterRaw):
- comb.append(reg.r.eq(self.interface.dat_i[:reg.size]))
+ comb.append(reg.r.eq(self.interface.dat_w[:reg.size]))
comb.append(reg.re.eq(sel & \
- self.interface.we_i & \
- (self.interface.adr_i[:nbits] == Constant(i, BV(nbits)))))
+ self.interface.we & \
+ (self.interface.adr[:nbits] == Constant(i, BV(nbits)))))
elif isinstance(reg, RegisterFields):
bwra = [Constant(i, BV(nbits))]
offset = 0
for field in reg.fields:
if field.access_bus == WRITE_ONLY or field.access_bus == READ_WRITE:
- bwra.append(field.storage.eq(self.interface.dat_i[offset:offset+field.size]))
+ bwra.append(field.storage.eq(self.interface.dat_w[offset:offset+field.size]))
offset += field.size
if len(bwra) > 1:
bwcases.append(bwra)
else:
raise TypeError
if bwcases:
- sync.append(If(sel & self.interface.we_i, Case(self.interface.adr_i[:nbits], *bwcases)))
+ sync.append(If(sel & self.interface.we, Case(self.interface.adr[:nbits], *bwcases)))
# Bus reads
brcases = []
for i, reg in enumerate(desc_exp):
if isinstance(reg, RegisterRaw):
- brcases.append([Constant(i, BV(nbits)), self.interface.dat_o.eq(reg.w)])
+ brcases.append([Constant(i, BV(nbits)), self.interface.dat_r.eq(reg.w)])
elif isinstance(reg, RegisterFields):
brs = []
reg_readable = False
@@ -56,16 +56,16 @@ def get_fragment(self):
brs.append(Constant(0, BV(field.size)))
if reg_readable:
if len(brs) > 1:
- brcases.append([Constant(i, BV(nbits)), self.interface.dat_o.eq(Cat(*brs))])
+ brcases.append([Constant(i, BV(nbits)), self.interface.dat_r.eq(Cat(*brs))])
else:
- brcases.append([Constant(i, BV(nbits)), self.interface.dat_o.eq(brs[0])])
+ brcases.append([Constant(i, BV(nbits)), self.interface.dat_r.eq(brs[0])])
else:
raise TypeError
if brcases:
- sync.append(self.interface.dat_o.eq(Constant(0, BV(8))))
- sync.append(If(sel, Case(self.interface.adr_i[:nbits], *brcases)))
+ sync.append(self.interface.dat_r.eq(Constant(0, BV(8))))
+ sync.append(If(sel, Case(self.interface.adr[:nbits], *brcases)))
else:
- comb.append(self.interface.dat_o.eq(Constant(0, BV(8))))
+ comb.append(self.interface.dat_r.eq(Constant(0, BV(8))))
# Device access
for reg in self.description:
View
11 migen/bus/simple.py
@@ -33,11 +33,12 @@ def __init__(self, master, slaves):
self.slaves = slaves
def get_fragment(self):
- s2m = master.desc.get_names(S_TO_M)
- m2s = master.desc.get_names(M_TO_S)
- comb = [getattr(slave, name).eq(getattr(master, name))
- for name in m2s for slave in self.slave]
- comb += [getattr(master, name).eq(
+ desc = self.master.desc
+ s2m = desc.get_names(S_TO_M)
+ m2s = desc.get_names(M_TO_S)
+ comb = [getattr(slave, name).eq(getattr(self.master, name))
+ for name in m2s for slave in self.slaves]
+ comb += [getattr(self.master, name).eq(
optree("|", [getattr(slave, name) for slave in self.slaves])
)
for name in s2m]

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