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  • 2 commits
  • 3 files changed
  • 0 commit comments
  • 1 contributor
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4 examples/basic_sim.py
@@ -5,7 +5,7 @@
class Counter:
def __init__(self):
self.ce = Signal()
- self.count = Signal(BV(4))
+ self.count = Signal(BV(37, True), reset=-5)
def do_simulation(self, s, cycle):
if cycle % 2:
@@ -22,6 +22,6 @@ def get_fragment(self):
def main():
dut = Counter()
sim = Simulator(dut.get_fragment(), Runner(), TopLevel("my.vcd"))
- sim.run(10)
+ sim.run(20)
main()
View
2  migen/fhdl/verilog.py
@@ -21,7 +21,7 @@ def _printexpr(ns, node):
if node.n >= 0:
return str(node.bv) + str(node.n)
else:
- return "-" + str(node.bv) + str(-self.n)
+ return "-" + str(node.bv) + str(-node.n)
elif isinstance(node, Signal):
return ns.get_name(node)
elif isinstance(node, _Operator):
View
11 migen/sim/generic.py
@@ -111,12 +111,17 @@ def rd(self, signal):
self.ipc.send(MessageRead(name))
reply = self.ipc.recv()
assert(isinstance(reply, MessageReadReply))
- # TODO: negative numbers + cleanup LSBs
- return reply.value
+ nbits = signal.bv.width
+ value = reply.value & (2**nbits - 1)
+ if signal.bv.signed and (value & 2**(nbits - 1)):
+ value -= 2**nbits
+ return value
def wr(self, signal, value):
name = self.top_level.top_name + "." \
+ self.top_level.dut_name + "." \
+ self.namespace.get_name(signal)
- # TODO: negative numbers
+ if value < 0:
+ value += 2**signal.bv.width
+ assert(value >= 0 and value < 2**signal.bv.width)
self.ipc.send(MessageWrite(name, value))

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