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  • 3 commits
  • 7 files changed
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  • 1 contributor
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1  examples/corelogic_conv.py
@@ -1,4 +1,3 @@
-from migen.fhdl import structure as f
from migen.fhdl import verilog
from migen.corelogic import roundrobin, divider
View
64 examples/lm32_inst.py
@@ -1,47 +1,47 @@
-from migen.fhdl import structure as f
+from migen.fhdl.structure import *
from migen.fhdl import verilog
class LM32:
def __init__(self):
- self.inst = f.Instance("lm32_top",
- [("I_ADR_O", f.BV(32)),
- ("I_DAT_O", f.BV(32)),
- ("I_SEL_O", f.BV(4)),
- ("I_CYC_O", f.BV(1)),
- ("I_STB_O", f.BV(1)),
- ("I_WE_O", f.BV(1)),
- ("I_CTI_O", f.BV(3)),
- ("I_LOCK_O", f.BV(1)),
- ("I_BTE_O", f.BV(1)),
- ("D_ADR_O", f.BV(32)),
- ("D_DAT_O", f.BV(32)),
- ("D_SEL_O", f.BV(4)),
- ("D_CYC_O", f.BV(1)),
- ("D_STB_O", f.BV(1)),
- ("D_WE_O", f.BV(1)),
- ("D_CTI_O", f.BV(3)),
- ("D_LOCK_O", f.BV(1)),
- ("D_BTE_O", f.BV(1))],
- [("interrupt", f.BV(32)),
- ("ext_break", f.BV(1)),
- ("I_DAT_I", f.BV(32)),
- ("I_ACK_I", f.BV(1)),
- ("I_ERR_I", f.BV(1)),
- ("I_RTY_I", f.BV(1)),
- ("D_DAT_I", f.BV(32)),
- ("D_ACK_I", f.BV(1)),
- ("D_ERR_I", f.BV(1)),
- ("D_RTY_I", f.BV(1))],
+ self.inst = Instance("lm32_top",
+ [("I_ADR_O", BV(32)),
+ ("I_DAT_O", BV(32)),
+ ("I_SEL_O", BV(4)),
+ ("I_CYC_O", BV(1)),
+ ("I_STB_O", BV(1)),
+ ("I_WE_O", BV(1)),
+ ("I_CTI_O", BV(3)),
+ ("I_LOCK_O", BV(1)),
+ ("I_BTE_O", BV(1)),
+ ("D_ADR_O", BV(32)),
+ ("D_DAT_O", BV(32)),
+ ("D_SEL_O", BV(4)),
+ ("D_CYC_O", BV(1)),
+ ("D_STB_O", BV(1)),
+ ("D_WE_O", BV(1)),
+ ("D_CTI_O", BV(3)),
+ ("D_LOCK_O", BV(1)),
+ ("D_BTE_O", BV(1))],
+ [("interrupt", BV(32)),
+ ("ext_break", BV(1)),
+ ("I_DAT_I", BV(32)),
+ ("I_ACK_I", BV(1)),
+ ("I_ERR_I", BV(1)),
+ ("I_RTY_I", BV(1)),
+ ("D_DAT_I", BV(32)),
+ ("D_ACK_I", BV(1)),
+ ("D_ERR_I", BV(1)),
+ ("D_RTY_I", BV(1))],
[],
"clk_i",
"rst_i",
"lm32")
def get_fragment(self):
- return f.Fragment(instances=[self.inst])
+ return Fragment(instances=[self.inst])
cpus = [LM32() for i in range(4)]
-frag = f.Fragment()
+frag = Fragment()
for cpu in cpus:
frag += cpu.get_fragment()
print(verilog.Convert(frag, set([cpus[0].inst.ins["interrupt"], cpus[0].inst.outs["I_WE_O"]])))
View
12 examples/simple_gpio.py
@@ -1,4 +1,4 @@
-from migen.fhdl import structure as f
+from migen.fhdl.structure import *
from migen.fhdl import verilog
from migen.bank import description, csrgen
@@ -11,11 +11,11 @@
ifield = description.Field(ireg, "val", ninputs, description.READ_ONLY, description.WRITE_ONLY)
# input path
-gpio_in = f.Signal(f.BV(ninputs), name="gpio_in")
-gpio_in_s = f.Signal(f.BV(ninputs), name="gpio_in_s") # synchronizer
-incomb = [f.Assign(ifield.dev_we, 1)]
-insync = [f.Assign(gpio_in_s, gpio_in), f.Assign(ifield.dev_w, gpio_in_s)]
-inf = f.Fragment(incomb, insync)
+gpio_in = Signal(BV(ninputs))
+gpio_in_s = Signal(BV(ninputs)) # synchronizer
+incomb = [ifield.dev_we.eq(1)]
+insync = [gpio_in_s.eq(gpio_in), ifield.dev_w.eq(gpio_in_s)]
+inf = Fragment(incomb, insync)
bank = csrgen.Bank([oreg, ireg])
f = bank.get_fragment() + inf
View
1  examples/wb_intercon/intercon_conv.py
@@ -1,5 +1,4 @@
from migen.fhdl import verilog
-from migen.fhdl import structure as f
from migen.bus import wishbone
m1 = wishbone.Master("m1")
View
12 migen/corelogic/divider.py
@@ -4,12 +4,12 @@ class Inst:
def __init__(self, w):
self.w = w
- start_i = Signal()
- dividend_i = Signal(BV(w))
- divisor_i = Signal(BV(w))
- ready_o = Signal()
- quotient_o = Signal(BV(w))
- remainder_o = Signal(BV(w))
+ self.start_i = Signal()
+ self.dividend_i = Signal(BV(w))
+ self.divisor_i = Signal(BV(w))
+ self.ready_o = Signal()
+ self.quotient_o = Signal(BV(w))
+ self.remainder_o = Signal(BV(w))
def get_fragment(self):
w = self.w
View
4 migen/corelogic/roundrobin.py
@@ -4,8 +4,8 @@ class Inst:
def __init__(self, n):
self.n = n
self.bn = bits_for(self.n-1)
- request = Signal(BV(self.n))
- grant = Signal(BV(self.bn))
+ self.request = Signal(BV(self.n))
+ self.grant = Signal(BV(self.bn))
def get_fragment(self):
cases = []
View
2  migen/fhdl/structure.py
@@ -128,7 +128,7 @@ def _cst(x):
def _make_signal_name():
frame = inspect.currentframe().f_back.f_back
line = inspect.getframeinfo(frame).code_context[0]
- m = re.match('[\t ]*([0-9A-Za-z_\.]+) =', line)
+ m = re.match('[\t ]*([0-9A-Za-z_\.]+)[\t ]*=', line)
if m is None: return None
name = m.group(1)
name = name.split('.')

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