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  • 2 commits
  • 2 files changed
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  • 1 contributor
Showing with 44 additions and 19 deletions.
  1. +8 −9 migen/actorlib/dma_asmi.py
  2. +36 −10 migen/actorlib/spi.py
View
17 migen/actorlib/dma_asmi.py
@@ -105,8 +105,7 @@ def __init__(self, port):
]
class _WriteSlot(Module):
- def __init__(self, port, n):
- self.load_data = Signal(port.hub.dw)
+ def __init__(self, port, load_data, n):
self.busy = Signal()
###
@@ -119,15 +118,15 @@ def __init__(self, port, n):
]
self.sync += [
- If(port.stb & port.ack & (port.tag_issue == (port.base + n)),
- self.busy.eq(1),
- data_reg.eq(self.load_data)
- ),
drive_data.eq(0),
If(port.get_call_expression(n),
self.busy.eq(0),
drive_data.eq(1)
- )
+ ),
+ If(port.stb & port.ack & (port.tag_issue == n),
+ self.busy.eq(1),
+ data_reg.eq(load_data)
+ ),
]
class OOOWriter(Module):
@@ -147,9 +146,9 @@ def __init__(self, port):
busy = 0
for i in range(len(port.slots)):
- write_slot = _WriteSlot(port, i)
+ write_slot = _WriteSlot(port, self.address_data.payload.d, i)
+ #write_slot = _WriteSlot(port, 0x12345678abad1deacafebabedeadbeef, i)
self.submodules += write_slot
- self.comb += write_slot.load_data.eq(self.address_data.payload.d)
busy = busy | write_slot.busy
self.comb += self.busy.eq(busy)
View
46 migen/actorlib/spi.py
@@ -115,17 +115,25 @@ def __init__(self, layout, depth=1024):
self._r_rd.status.eq(rp.dat_r)
]
-class DMAReadController(Module):
- def __init__(self, bus_accessor, mode, base_reset=0, length_reset=0):
- bus_aw = len(bus_accessor.address.payload.a)
- bus_dw = len(bus_accessor.data.payload.d)
- alignment_bits = bits_for(bus_dw//8) - 1
-
+class _DMAController(Module):
+ def __init__(self, bus_accessor, bus_aw, bus_dw, mode, base_reset=0, length_reset=0):
+ self.alignment_bits = bits_for(bus_dw//8) - 1
layout = [
- ("length", bus_aw + alignment_bits, length_reset, alignment_bits),
- ("base", bus_aw + alignment_bits, base_reset, alignment_bits)
+ ("length", bus_aw + self.alignment_bits, length_reset, self.alignment_bits),
+ ("base", bus_aw + self.alignment_bits, base_reset, self.alignment_bits)
]
self.generator = SingleGenerator(layout, mode)
+ self.r_busy = CSRStatus()
+
+ def get_csrs(self):
+ return self.generator.get_csrs() + [self.r_busy]
+
+class DMAReadController(_DMAController):
+ def __init__(self, bus_accessor, *args, **kwargs):
+ bus_aw = len(bus_accessor.address.payload.a)
+ bus_dw = len(bus_accessor.data.payload.d)
+ _DMAController.__init__(self, bus_accessor, bus_aw, bus_dw, *args, **kwargs)
+
g = DataFlowGraph()
g.add_pipeline(self.generator,
misc.IntSequence(bus_aw, bus_aw),
@@ -137,6 +145,24 @@ def __init__(self, bus_accessor, mode, base_reset=0, length_reset=0):
self.data = comp_actor.q
self.busy = comp_actor.busy
+ self.comb += self.r_busy.status.eq(self.busy)
+
+class DMAWriteController(_DMAController):
+ def __init__(self, bus_accessor, *args, **kwargs):
+ bus_aw = len(bus_accessor.address_data.payload.a)
+ bus_dw = len(bus_accessor.address_data.payload.d)
+ _DMAController.__init__(self, bus_accessor, bus_aw, bus_dw, *args, **kwargs)
- def get_csrs(self):
- return self.generator.get_csrs()
+ g = DataFlowGraph()
+ adr_buffer = AbstractActor(plumbing.Buffer)
+ g.add_pipeline(self.generator,
+ misc.IntSequence(bus_aw, bus_aw),
+ adr_buffer)
+ g.add_connection(adr_buffer, bus_accessor, sink_subr=["a"])
+ g.add_connection(AbstractActor(plumbing.Buffer), bus_accessor, sink_subr=["d"])
+ comp_actor = CompositeActor(g)
+ self.submodules += comp_actor
+
+ self.data = comp_actor.d
+ self.busy = comp_actor.busy
+ self.comb += self.r_busy.status.eq(self.busy)

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