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17  migen/actorlib/dma_asmi.py
@@ -105,8 +105,7 @@ def __init__(self, port):
105 105
 		]
106 106
 
107 107
 class _WriteSlot(Module):
108  
-	def __init__(self, port, n):
109  
-		self.load_data = Signal(port.hub.dw)
  108
+	def __init__(self, port, load_data, n):
110 109
 		self.busy = Signal()
111 110
 
112 111
 		###
@@ -119,15 +118,15 @@ def __init__(self, port, n):
119 118
 		]
120 119
 
121 120
 		self.sync += [
122  
-			If(port.stb & port.ack & (port.tag_issue == (port.base + n)),
123  
-				self.busy.eq(1),
124  
-				data_reg.eq(self.load_data)
125  
-			),
126 121
 			drive_data.eq(0),
127 122
 			If(port.get_call_expression(n),
128 123
 				self.busy.eq(0),
129 124
 				drive_data.eq(1)
130  
-			)
  125
+			),
  126
+			If(port.stb & port.ack & (port.tag_issue == n),
  127
+				self.busy.eq(1),
  128
+				data_reg.eq(load_data)
  129
+			),
131 130
 		]
132 131
 
133 132
 class OOOWriter(Module):
@@ -147,9 +146,9 @@ def __init__(self, port):
147 146
 
148 147
 		busy = 0
149 148
 		for i in range(len(port.slots)):
150  
-			write_slot = _WriteSlot(port, i)
  149
+			write_slot = _WriteSlot(port, self.address_data.payload.d, i)
  150
+			#write_slot = _WriteSlot(port, 0x12345678abad1deacafebabedeadbeef, i)
151 151
 			self.submodules += write_slot
152  
-			self.comb += write_slot.load_data.eq(self.address_data.payload.d)
153 152
 			busy = busy | write_slot.busy
154 153
 		self.comb += self.busy.eq(busy)
155 154
 
46  migen/actorlib/spi.py
@@ -115,17 +115,25 @@ def __init__(self, layout, depth=1024):
115 115
 			self._r_rd.status.eq(rp.dat_r)
116 116
 		]
117 117
 
118  
-class DMAReadController(Module):
119  
-	def __init__(self, bus_accessor, mode, base_reset=0, length_reset=0):
120  
-		bus_aw = len(bus_accessor.address.payload.a)
121  
-		bus_dw = len(bus_accessor.data.payload.d)
122  
-		alignment_bits = bits_for(bus_dw//8) - 1
123  
-
  118
+class _DMAController(Module):
  119
+	def __init__(self, bus_accessor, bus_aw, bus_dw, mode, base_reset=0, length_reset=0):
  120
+		self.alignment_bits = bits_for(bus_dw//8) - 1
124 121
 		layout = [
125  
-			("length", bus_aw + alignment_bits, length_reset, alignment_bits),
126  
-			("base", bus_aw + alignment_bits, base_reset, alignment_bits)
  122
+			("length", bus_aw + self.alignment_bits, length_reset, self.alignment_bits),
  123
+			("base", bus_aw + self.alignment_bits, base_reset, self.alignment_bits)
127 124
 		]
128 125
 		self.generator = SingleGenerator(layout, mode)
  126
+		self.r_busy = CSRStatus()
  127
+
  128
+	def get_csrs(self):
  129
+		return self.generator.get_csrs() + [self.r_busy]
  130
+
  131
+class DMAReadController(_DMAController):
  132
+	def __init__(self, bus_accessor, *args, **kwargs):
  133
+		bus_aw = len(bus_accessor.address.payload.a)
  134
+		bus_dw = len(bus_accessor.data.payload.d)
  135
+		_DMAController.__init__(self, bus_accessor, bus_aw, bus_dw, *args, **kwargs)
  136
+		
129 137
 		g = DataFlowGraph()
130 138
 		g.add_pipeline(self.generator,
131 139
 			misc.IntSequence(bus_aw, bus_aw),
@@ -137,6 +145,24 @@ def __init__(self, bus_accessor, mode, base_reset=0, length_reset=0):
137 145
 
138 146
 		self.data = comp_actor.q
139 147
 		self.busy = comp_actor.busy
  148
+		self.comb += self.r_busy.status.eq(self.busy)
  149
+
  150
+class DMAWriteController(_DMAController):
  151
+	def __init__(self, bus_accessor, *args, **kwargs):
  152
+		bus_aw = len(bus_accessor.address_data.payload.a)
  153
+		bus_dw = len(bus_accessor.address_data.payload.d)
  154
+		_DMAController.__init__(self, bus_accessor, bus_aw, bus_dw, *args, **kwargs)
140 155
 		
141  
-	def get_csrs(self):
142  
-		return self.generator.get_csrs()
  156
+		g = DataFlowGraph()
  157
+		adr_buffer = AbstractActor(plumbing.Buffer)
  158
+		g.add_pipeline(self.generator,
  159
+			misc.IntSequence(bus_aw, bus_aw),
  160
+			adr_buffer)
  161
+		g.add_connection(adr_buffer, bus_accessor, sink_subr=["a"])
  162
+		g.add_connection(AbstractActor(plumbing.Buffer), bus_accessor, sink_subr=["d"])
  163
+		comp_actor = CompositeActor(g)
  164
+		self.submodules += comp_actor
  165
+
  166
+		self.data = comp_actor.d
  167
+		self.busy = comp_actor.busy
  168
+		self.comb += self.r_busy.status.eq(self.busy)

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