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  • 2 commits
  • 4 files changed
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  • 1 contributor
Showing with 16 additions and 9 deletions.
  1. +1 −1 doc/migen.txt
  2. +5 −3 examples/memory.py
  3. +1 −1 migen/fhdl/structure.py
  4. +9 −4 migen/fhdl/verilog_mem_behavioral.py
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2 doc/migen.txt
@@ -310,7 +310,7 @@ Each port description contains:
in each sub-word. If it is set to 0, the port is using whole-word
writes only and the width of the write enable signal must be 1. This
parameter is ignored if there is no write enable signal.
- - the mode of the port (default READ_FIRST, ignored for asynchronous
+ - the mode of the port (default WRITE_FIRST, ignored for asynchronous
ports). It can be:
* READ_FIRST: during a write, the previous value is read.
* WRITE_FIRST: the written value is returned.
View
8 examples/memory.py
@@ -9,13 +9,15 @@
d1 = Signal(BV(w))
we1 = Signal(BV(4))
dw1 = Signal(BV(w))
-p1 = MemoryPort(a1, d1, we1, dw1, we_granularity=8, mode=WRITE_FIRST)
+re = Signal()
+p1 = MemoryPort(a1, d1, we1, dw1, we_granularity=8)
a2 = Signal(BV(d_b))
d2 = Signal(BV(w))
-p2 = MemoryPort(a2, d2)
+re2 = Signal()
+p2 = MemoryPort(a2, d2, re=re2)
mem = Memory(w, d, p1, p2, init=[5, 18, 32])
f = Fragment(memories=[mem])
-v = verilog.convert(f, ios={a1, d1, we1, dw1, a2, d2})
+v = verilog.convert(f, ios={a1, d1, we1, dw1, a2, d2, re2})
print(v)
View
2 migen/fhdl/structure.py
@@ -232,7 +232,7 @@ def __hash__(self):
class MemoryPort:
def __init__(self, adr, dat_r, we=None, dat_w=None,
- async_read=False, re=None, we_granularity=0, mode=READ_FIRST):
+ async_read=False, re=None, we_granularity=0, mode=WRITE_FIRST):
self.adr = adr
self.dat_r = dat_r
self.we = we
View
13 migen/fhdl/verilog_mem_behavioral.py
@@ -41,14 +41,19 @@ def handler(memory, ns, clk):
r += "\t\t" + gn(storage) + "[" + gn(port.adr) + "] <= " + gn(port.dat_w) + ";\n"
if not port.async_read:
if port.mode == WRITE_FIRST and port.we is not None:
- r += "\t" + gn(adr_regs[id(port)]) + " <= " + gn(port.adr) + ";\n"
+ rd = "\t" + gn(adr_regs[id(port)]) + " <= " + gn(port.adr) + ";\n"
else:
bassign = gn(data_regs[id(port)]) + " <= " + gn(storage) + "[" + gn(port.adr) + "];\n"
if port.mode == READ_FIRST or port.we is None:
- r += "\t" + bassign
+ rd = "\t" + bassign
elif port.mode == NO_CHANGE:
- r += "\tif (!" + gn(port.we) + ")\n"
- r += "\t\t" + bassign
+ rd = "\tif (!" + gn(port.we) + ")\n" \
+ + "\t\t" + bassign
+ if port.re is None:
+ r += rd
+ else:
+ r += "\tif (" + gn(port.re) + ")\n"
+ r += "\t" + rd.replace("\n\t", "\n\t\t")
r += "end\n\n"
for port in memory.ports:

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