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2  examples/basic/complex.py
... ...
@@ -1,4 +1,4 @@
1  
-from migen.corelogic.complex import *
  1
+from migen.genlib.complex import *
2 2
 from migen.fhdl import verilog
3 3
 
4 4
 w = Complex(32, 42)
2  examples/basic/fsm.py
... ...
@@ -1,6 +1,6 @@
1 1
 from migen.fhdl.structure import *
2 2
 from migen.fhdl import verilog
3  
-from migen.corelogic.fsm import FSM
  3
+from migen.genlib.fsm import FSM
4 4
 
5 5
 s = Signal()
6 6
 myfsm = FSM("FOO", "BAR")
2  examples/basic/namer.py
... ...
@@ -1,6 +1,6 @@
1 1
 from migen.fhdl.structure import *
2 2
 from migen.fhdl import verilog
3  
-from migen.corelogic.misc import optree
  3
+from migen.genlib.misc import optree
4 4
 
5 5
 def gen_list(n):
6 6
 	s = [Signal() for i in range(n)]
2  examples/basic/two_dividers.py
... ...
@@ -1,5 +1,5 @@
1 1
 from migen.fhdl import verilog
2  
-from migen.corelogic import divider
  2
+from migen.genlib import divider
3 3
 
4 4
 d1 = divider.Divider(16)
5 5
 d2 = divider.Divider(16)
2  examples/basic/using_record.py
... ...
@@ -1,5 +1,5 @@
1 1
 from migen.fhdl.structure import *
2  
-from migen.corelogic.record import *
  2
+from migen.genlib.record import *
3 3
 
4 4
 L = [
5 5
 	("x", 10, 8),
8  examples/sim/fir.py
@@ -7,7 +7,7 @@
7 7
 
8 8
 from migen.fhdl.structure import *
9 9
 from migen.fhdl import verilog
10  
-from migen.corelogic.misc import optree
  10
+from migen.genlib.misc import optree
11 11
 from migen.fhdl import autofragment
12 12
 from migen.sim.generic import Simulator, PureSimulable
13 13
 
@@ -52,18 +52,18 @@ def do_simulation(self, s):
52 52
 
53 53
 def main():
54 54
 	# Compute filter coefficients with SciPy.
55  
-	coef = signal.remez(80, [0, 0.1, 0.1, 0.5], [1, 0])
  55
+	coef = signal.remez(30, [0, 0.1, 0.2, 0.4, 0.45, 0.5], [0, 1, 0])
56 56
 	fir = FIR(coef)
57 57
 	
58 58
 	# Simulate for different frequencies and concatenate
59 59
 	# the results.
60 60
 	in_signals = []
61 61
 	out_signals = []
62  
-	for frequency in [0.05, 0.07, 0.1, 0.15, 0.2]:
  62
+	for frequency in [0.05, 0.1, 0.25]:
63 63
 		tb = TB(fir, frequency)
64 64
 		fragment = autofragment.from_local()
65 65
 		sim = Simulator(fragment)
66  
-		sim.run(100)
  66
+		sim.run(200)
67 67
 		del sim
68 68
 		in_signals += tb.inputs
69 69
 		out_signals += tb.outputs
2  migen/actorlib/dma_asmi.py
... ...
@@ -1,6 +1,6 @@
1 1
 from migen.fhdl.structure import *
2 2
 from migen.flow.actor import *
3  
-from migen.corelogic.buffers import ReorderBuffer
  3
+from migen.genlib.buffers import ReorderBuffer
4 4
 
5 5
 class SequentialReader(Actor):
6 6
 	def __init__(self, port):
4  migen/actorlib/misc.py
... ...
@@ -1,6 +1,6 @@
1 1
 from migen.fhdl.structure import *
2  
-from migen.corelogic.record import *
3  
-from migen.corelogic.fsm import *
  2
+from migen.genlib.record import *
  3
+from migen.genlib.fsm import *
4 4
 from migen.flow.actor import *
5 5
 
6 6
 # Generates integers from start to maximum-1
2  migen/bank/eventmanager.py
... ...
@@ -1,6 +1,6 @@
1 1
 from migen.fhdl.structure import *
2 2
 from migen.bank.description import *
3  
-from migen.corelogic.misc import optree
  3
+from migen.genlib.misc import optree
4 4
 
5 5
 class EventSource:
6 6
 	def __init__(self):
2  migen/bus/asmibus.py
... ...
@@ -1,5 +1,5 @@
1 1
 from migen.fhdl.structure import *
2  
-from migen.corelogic.misc import optree
  2
+from migen.genlib.misc import optree
3 3
 from migen.bus.transactions import *
4 4
 from migen.sim.generic import Proxy, PureSimulable
5 5
 
2  migen/bus/simple.py
... ...
@@ -1,5 +1,5 @@
1 1
 from migen.fhdl.structure import *
2  
-from migen.corelogic.misc import optree
  2
+from migen.genlib.misc import optree
3 3
 
4 4
 (S_TO_M, M_TO_S) = range(2)
5 5
 
4  migen/bus/wishbone.py
... ...
@@ -1,7 +1,7 @@
1 1
 from migen.fhdl.structure import *
2 2
 from migen.fhdl.specials import Memory
3  
-from migen.corelogic import roundrobin
4  
-from migen.corelogic.misc import optree
  3
+from migen.genlib import roundrobin
  4
+from migen.genlib.misc import optree
5 5
 from migen.bus.simple import *
6 6
 from migen.bus.transactions import *
7 7
 from migen.sim.generic import Proxy, PureSimulable
6  migen/bus/wishbone2asmi.py
... ...
@@ -1,9 +1,9 @@
1 1
 from migen.fhdl.structure import *
2 2
 from migen.fhdl.specials import Memory
3 3
 from migen.bus import wishbone
4  
-from migen.corelogic.fsm import FSM
5  
-from migen.corelogic.misc import split, displacer, chooser
6  
-from migen.corelogic.record import Record
  4
+from migen.genlib.fsm import FSM
  5
+from migen.genlib.misc import split, displacer, chooser
  6
+from migen.genlib.record import Record
7 7
 
8 8
 # cachesize (in 32-bit words) is the size of the data store, must be a power of 2
9 9
 class WB2ASMI:
2  migen/bus/wishbone2csr.py
... ...
@@ -1,7 +1,7 @@
1 1
 from migen.bus import wishbone
2 2
 from migen.bus import csr
3 3
 from migen.fhdl.structure import *
4  
-from migen.corelogic.misc import timeline
  4
+from migen.genlib.misc import timeline
5 5
 
6 6
 class WB2CSR:
7 7
 	def __init__(self):
4  migen/flow/actor.py
... ...
@@ -1,6 +1,6 @@
1 1
 from migen.fhdl.structure import *
2  
-from migen.corelogic.misc import optree
3  
-from migen.corelogic.record import *
  2
+from migen.genlib.misc import optree
  3
+from migen.genlib.record import *
4 4
 
5 5
 class Endpoint:
6 6
 	def __init__(self, token):
2  migen/flow/network.py
... ...
@@ -1,7 +1,7 @@
1 1
 from networkx import MultiDiGraph
2 2
 
3 3
 from migen.fhdl.structure import *
4  
-from migen.corelogic.misc import optree
  4
+from migen.genlib.misc import optree
5 5
 from migen.flow.actor import *
6 6
 from migen.flow import plumbing
7 7
 from migen.flow.isd import DFGReporter
4  migen/flow/plumbing.py
... ...
@@ -1,7 +1,7 @@
1 1
 from migen.fhdl.structure import *
2 2
 from migen.flow.actor import *
3  
-from migen.corelogic.record import *
4  
-from migen.corelogic.misc import optree
  3
+from migen.genlib.record import *
  4
+from migen.genlib.misc import optree
5 5
 
6 6
 class Buffer(PipelinedActor):
7 7
 	def __init__(self, layout):
0  migen/corelogic/__init__.py → migen/genlib/__init__.py
File renamed without changes
0  migen/corelogic/buffers.py → migen/genlib/buffers.py
File renamed without changes
0  migen/corelogic/complex.py → migen/genlib/complex.py
File renamed without changes
0  migen/corelogic/divider.py → migen/genlib/divider.py
File renamed without changes
0  migen/corelogic/fsm.py → migen/genlib/fsm.py
File renamed without changes
0  migen/corelogic/misc.py → migen/genlib/misc.py
File renamed without changes
0  migen/corelogic/record.py → migen/genlib/record.py
File renamed without changes
0  migen/corelogic/roundrobin.py → migen/genlib/roundrobin.py
File renamed without changes
2  migen/pytholite/fsm.py
... ...
@@ -1,5 +1,5 @@
1 1
 from migen.fhdl import visit as fhdl
2  
-from migen.corelogic.fsm import FSM
  2
+from migen.genlib.fsm import FSM
3 3
 
4 4
 class AbstractNextState:
5 5
 	def __init__(self, target_state):

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