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6  examples/basic/psync.py
@@ -4,10 +4,10 @@
4 4
 from migen.genlib.cdc import *
5 5
 
6 6
 class XilinxMultiRegImpl(MultiRegImpl):
7  
-	def get_fragment(self):
8  
-		disable_srl = set(SynthesisDirective("attribute shreg_extract of {r} is no", r=r)
  7
+	def __init__(self, *args, **kwargs):
  8
+		MultiRegImpl.__init__(self, *args, **kwargs)
  9
+		self.specials += set(SynthesisDirective("attribute shreg_extract of {r} is no", r=r)
9 10
 			for r in self.regs)
10  
-		return MultiRegImpl.get_fragment(self) + Fragment(specials=disable_srl)
11 11
 
12 12
 class XilinxMultiReg:
13 13
 	@staticmethod
16  examples/sim/basic1.py
@@ -6,9 +6,13 @@
6 6
 
7 7
 # Our simple counter, which increments at every cycle
8 8
 # and prints its current value in simulation.
9  
-class Counter:
  9
+class Counter(Module):
10 10
 	def __init__(self):
11 11
 		self.count = Signal(4)
  12
+
  13
+		# At each cycle, increase the value of the count signal.
  14
+		# We do it with convertible/synthesizable FHDL code.
  15
+		self.sync += self.count.eq(self.count + 1)
12 16
 	
13 17
 	# This function will be called at every cycle.
14 18
 	def do_simulation(self, s):
@@ -19,19 +23,11 @@ def do_simulation(self, s):
19 23
 		# Count: 2
20 24
 		# ...
21 25
 		print("Count: " + str(s.rd(self.count)))
22  
-	
23  
-	def get_fragment(self):
24  
-		# At each cycle, increase the value of the count signal.
25  
-		# We do it with convertible/synthesizable FHDL code.
26  
-		sync = [self.count.eq(self.count + 1)]
27  
-		# List our simulation function in the fragment.
28  
-		sim = [self.do_simulation]
29  
-		return Fragment(sync=sync, sim=sim)
30 26
 
31 27
 def main():
32 28
 	dut = Counter()
33 29
 	# We do not specify a top-level nor runner object, and use the defaults.
34  
-	sim = Simulator(dut.get_fragment())
  30
+	sim = Simulator(dut)
35 31
 	# Since we do not use sim.interrupt, limit the simulation
36 32
 	# to some number of cycles.
37 33
 	sim.run(20)
11  examples/sim/basic2.py
@@ -7,11 +7,13 @@
7 7
 # A slightly improved counter.
8 8
 # Has a clock enable (CE) signal, counts on more bits
9 9
 # and resets with a negative number.
10  
-class Counter:
  10
+class Counter(Module):
11 11
 	def __init__(self):
12 12
 		self.ce = Signal()
13 13
 		# Demonstrate negative numbers and signals larger than 32 bits.
14 14
 		self.count = Signal((37, True), reset=-5)
  15
+
  16
+		self.sync += If(self.ce, self.count.eq(self.count + 1))
15 17
 	
16 18
 	def do_simulation(self, s):
17 19
 		# Only assert CE every second cycle.
@@ -35,17 +37,12 @@ def do_simulation(self, s):
35 37
 	# Cycle: 3 Count: -4
36 38
 	# Cycle: 4 Count: -3
37 39
 	# ...
38  
-	
39  
-	def get_fragment(self):
40  
-		sync = [If(self.ce, self.count.eq(self.count + 1))]
41  
-		sim = [self.do_simulation]
42  
-		return Fragment(sync=sync, sim=sim)
43 40
 
44 41
 def main():
45 42
 	dut = Counter()
46 43
 	# Instantiating the generic top-level ourselves lets us
47 44
 	# specify a VCD output file.
48  
-	sim = Simulator(dut.get_fragment(), TopLevel("my.vcd"))
  45
+	sim = Simulator(dut, TopLevel("my.vcd"))
49 46
 	sim.run(20)
50 47
 
51 48
 main()
9  examples/sim/memory.py
@@ -4,11 +4,11 @@
4 4
 from migen.fhdl.std import *
5 5
 from migen.sim.generic import Simulator
6 6
 
7  
-class Mem:
  7
+class Mem(Module):
8 8
 	def __init__(self):
9 9
 		# Initialize the beginning of the memory with integers
10 10
 		# from 0 to 19.
11  
-		self.mem = Memory(16, 2**12, init=list(range(20)))
  11
+		self.specials.mem = Memory(16, 2**12, init=list(range(20)))
12 12
 	
13 13
 	def do_simulation(self, s):
14 14
 		# Read the memory. Use the cycle counter as address.
@@ -22,13 +22,10 @@ def do_simulation(self, s):
22 22
 		# Demonstrate how to interrupt the simulator.
23 23
 		if value == 10:
24 24
 			s.interrupt = True
25  
-	
26  
-	def get_fragment(self):
27  
-		return Fragment(specials={self.mem}, sim=[self.do_simulation])
28 25
 
29 26
 def main():
30 27
 	dut = Mem()
31  
-	sim = Simulator(dut.get_fragment())
  28
+	sim = Simulator(dut)
32 29
 	# No need for a cycle limit here, we use sim.interrupt instead.
33 30
 	sim.run()
34 31
 
87  migen/genlib/buffers.py
... ...
@@ -1,87 +0,0 @@
1  
-from migen.fhdl.std import *
2  
-
3  
-class ReorderSlot:
4  
-	def __init__(self, tag_width, data_width):
5  
-		self.wait_data = Signal()
6  
-		self.has_data = Signal()
7  
-		self.tag = Signal(tag_width)
8  
-		self.data = Signal(data_width)
9  
-
10  
-class ReorderBuffer:
11  
-	def __init__(self, tag_width, data_width, depth):
12  
-		self.depth = depth
13  
-		
14  
-		# issue
15  
-		self.can_issue = Signal()
16  
-		self.issue = Signal()
17  
-		self.tag_issue = Signal(tag_width)
18  
-		
19  
-		# call
20  
-		self.call = Signal()
21  
-		self.tag_call = Signal(tag_width)
22  
-		self.data_call = Signal(data_width)
23  
-		
24  
-		# readback
25  
-		self.can_read = Signal()
26  
-		self.read = Signal()
27  
-		self.data_read = Signal(data_width)
28  
-		
29  
-		self._empty_count = Signal(max=self.depth+1, reset=self.depth)
30  
-		self._produce = Signal(max=self.depth)
31  
-		self._consume = Signal(max=self.depth)
32  
-		self._slots = Array(ReorderSlot(tag_width, data_width)
33  
-			for n in range(self.depth))
34  
-	
35  
-	def get_fragment(self):
36  
-		# issue
37  
-		comb = [
38  
-			self.can_issue.eq(self._empty_count != 0)
39  
-		]
40  
-		sync = [
41  
-			If(self.issue & self.can_issue,
42  
-				self._empty_count.eq(self._empty_count - 1),
43  
-				If(self._produce == self.depth - 1,
44  
-					self._produce.eq(0)
45  
-				).Else(
46  
-					self._produce.eq(self._produce + 1)
47  
-				),
48  
-				self._slots[self._produce].wait_data.eq(1),
49  
-				self._slots[self._produce].tag.eq(self.tag_issue)
50  
-			)
51  
-		]
52  
-		
53  
-		# call
54  
-		for n, slot in enumerate(self._slots):
55  
-			sync.append(
56  
-				If(self.call & slot.wait_data & (self.tag_call == slot.tag),
57  
-					slot.wait_data.eq(0),
58  
-					slot.has_data.eq(1),
59  
-					slot.data.eq(self.data_call)
60  
-				)
61  
-			)
62  
-		
63  
-		# readback
64  
-		comb += [
65  
-			self.can_read.eq(self._slots[self._consume].has_data),
66  
-			self.data_read.eq(self._slots[self._consume].data)
67  
-		]
68  
-		sync += [
69  
-			If(self.read & self.can_read,
70  
-				self._empty_count.eq(self._empty_count + 1),
71  
-				If(self._consume == self.depth - 1,
72  
-					self._consume.eq(0)
73  
-				).Else(
74  
-					self._consume.eq(self._consume + 1)
75  
-				),
76  
-				self._slots[self._consume].has_data.eq(0)
77  
-			)
78  
-		]
79  
-		
80  
-		# do not touch empty count when issuing and reading at the same time
81  
-		sync += [
82  
-			If(self.issue & self.can_issue & self.read & self.can_read,
83  
-				self._empty_count.eq(self._empty_count)
84  
-			)
85  
-		]
86  
-		
87  
-		return Fragment(comb, sync)
27  migen/genlib/cdc.py
@@ -58,29 +58,24 @@ def list_clock_domains(self):
58 58
 	def lower(dr):
59 59
 		return MultiRegImpl(dr.i, dr.o, dr.odomain, dr.n)
60 60
 
61  
-class PulseSynchronizer:
  61
+class PulseSynchronizer(Module):
62 62
 	def __init__(self, idomain, odomain):
63  
-		self.idomain = idomain
64  
-		self.odomain = odomain
65 63
 		self.i = Signal()
66 64
 		self.o = Signal()
67 65
 
68  
-	def get_fragment(self):
  66
+		###
  67
+
69 68
 		toggle_i = Signal()
70 69
 		toggle_o = Signal()
71 70
 		toggle_o_r = Signal()
72  
-		sync_i = [
73  
-			If(self.i, toggle_i.eq(~toggle_i))
74  
-		]
75  
-		sync_o = [
76  
-			toggle_o_r.eq(toggle_o)
77  
-		]
78  
-		comb = [
79  
-			self.o.eq(toggle_o ^ toggle_o_r)
80  
-		]
81  
-		return Fragment(comb, 
82  
-			{self.idomain: sync_i, self.odomain: sync_o},
83  
-			specials={MultiReg(toggle_i, toggle_o, self.odomain)})
  71
+
  72
+		sync_i = getattr(self.sync, idomain)
  73
+		sync_o = getattr(self.sync, odomain)
  74
+		
  75
+		sync_i += If(self.i, toggle_i.eq(~toggle_i))
  76
+		self.specials += MultiReg(toggle_i, toggle_o, odomain)
  77
+		sync_o += toggle_o_r.eq(toggle_o)
  78
+		self.comb += self.o.eq(toggle_o ^ toggle_o_r)
84 79
 
85 80
 class GrayCounter(Module):
86 81
 	def __init__(self, width):
76  migen/genlib/rob.py
... ...
@@ -0,0 +1,76 @@
  1
+from migen.fhdl.std import *
  2
+
  3
+class ReorderSlot:
  4
+	def __init__(self, tag_width, data_width):
  5
+		self.wait_data = Signal()
  6
+		self.has_data = Signal()
  7
+		self.tag = Signal(tag_width)
  8
+		self.data = Signal(data_width)
  9
+
  10
+class ReorderBuffer(Module):
  11
+	def __init__(self, tag_width, data_width, depth):
  12
+		# issue
  13
+		self.can_issue = Signal()
  14
+		self.issue = Signal()
  15
+		self.tag_issue = Signal(tag_width)
  16
+		
  17
+		# call
  18
+		self.call = Signal()
  19
+		self.tag_call = Signal(tag_width)
  20
+		self.data_call = Signal(data_width)
  21
+		
  22
+		# readback
  23
+		self.can_read = Signal()
  24
+		self.read = Signal()
  25
+		self.data_read = Signal(data_width)
  26
+	
  27
+		###
  28
+
  29
+		empty_count = Signal(max=depth+1, reset=depth)
  30
+		produce = Signal(max=depth)
  31
+		consume = Signal(max=depth)
  32
+		slots = Array(ReorderSlot(tag_width, data_width)
  33
+			for n in range(depth))
  34
+
  35
+		# issue
  36
+		self.comb += self.can_issue.eq(empty_count != 0)
  37
+		self.sync += If(self.issue & self.can_issue,
  38
+				empty_count.eq(empty_count - 1),
  39
+				If(produce == depth - 1,
  40
+					produce.eq(0)
  41
+				).Else(
  42
+					produce.eq(produce + 1)
  43
+				),
  44
+				slots[produce].wait_data.eq(1),
  45
+				slots[produce].tag.eq(self.tag_issue)
  46
+			)
  47
+		
  48
+		# call
  49
+		for n, slot in enumerate(slots):
  50
+			self.sync += If(self.call & slot.wait_data & (self.tag_call == slot.tag),
  51
+					slot.wait_data.eq(0),
  52
+					slot.has_data.eq(1),
  53
+					slot.data.eq(self.data_call)
  54
+				)
  55
+		
  56
+		# readback
  57
+		self.comb += [
  58
+			self.can_read.eq(slots[consume].has_data),
  59
+			self.data_read.eq(slots[consume].data)
  60
+		]
  61
+		self.sync += [
  62
+			If(self.read & self.can_read,
  63
+				empty_count.eq(empty_count + 1),
  64
+				If(consume == depth - 1,
  65
+					consume.eq(0)
  66
+				).Else(
  67
+					consume.eq(consume + 1)
  68
+				),
  69
+				slots[consume].has_data.eq(0)
  70
+			)
  71
+		]
  72
+		
  73
+		# do not touch empty count when issuing and reading at the same time
  74
+		self.sync += If(self.issue & self.can_issue & self.read & self.can_read,
  75
+				empty_count.eq(empty_count)
  76
+			)

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