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33  migen/actorlib/spi.py
@@ -40,8 +40,7 @@ def _create_registers_assign(layout, target, atomic, prefix=""):
40 40
 				alignment = element[3]
41 41
 			else:
42 42
 				alignment = 0
43  
-			reg = RegisterField(prefix + name, nbits + alignment,
44  
-				reset=reset, atomic_write=atomic)
  43
+			reg = RegisterField(nbits + alignment, reset=reset, atomic_write=atomic, name=prefix + name)
45 44
 			registers.append(reg)
46 45
 			assigns.append(getattr(target, name).eq(reg.field.r[alignment:]))
47 46
 	return registers, assigns
@@ -57,11 +56,11 @@ def __init__(self, layout, mode):
57 56
 		if mode == MODE_EXTERNAL:
58 57
 			self.trigger = Signal()
59 58
 		elif mode == MODE_SINGLE_SHOT:
60  
-			shoot = RegisterRaw("shoot")
  59
+			shoot = RegisterRaw()
61 60
 			self._registers.insert(0, shoot)
62 61
 			self.trigger = shoot.re
63 62
 		elif mode == MODE_CONTINUOUS:
64  
-			enable = RegisterField("enable")
  63
+			enable = RegisterField()
65 64
 			self._registers.insert(0, enable)
66 65
 			self.trigger = enable.field.r
67 66
 		else:
@@ -86,13 +85,13 @@ def __init__(self, layout, depth=1024):
86 85
 		self._depth = depth
87 86
 		self._dw = sum(len(s) for s in self.token("sink").flatten())
88 87
 		
89  
-		self._reg_wa = RegisterField("write_address", bits_for(self._depth-1), access_bus=READ_WRITE, access_dev=READ_WRITE)
90  
-		self._reg_wc = RegisterField("write_count", bits_for(self._depth), access_bus=READ_WRITE, access_dev=READ_WRITE, atomic_write=True)
91  
-		self._reg_ra = RegisterField("read_address", bits_for(self._depth-1), access_bus=READ_WRITE, access_dev=READ_ONLY)
92  
-		self._reg_rd = RegisterField("read_data", self._dw, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
  88
+		self._r_wa = RegisterField(bits_for(self._depth-1), READ_WRITE, READ_WRITE)
  89
+		self._r_wc = RegisterField(bits_for(self._depth), READ_WRITE, READ_WRITE, atomic_write=True)
  90
+		self._r_ra = RegisterField(bits_for(self._depth-1), READ_WRITE, READ_ONLY)
  91
+		self._r_rd = RegisterField(self._dw, READ_ONLY, WRITE_ONLY)
93 92
 	
94 93
 	def get_registers(self):
95  
-		return [self._reg_wa, self._reg_wc, self._reg_ra, self._reg_rd]
  94
+		return [self._r_wa, self._r_wc, self._r_ra, self._r_rd]
96 95
 	
97 96
 	def get_fragment(self):
98 97
 		mem = Memory(self._dw, self._depth)
@@ -100,22 +99,22 @@ def get_fragment(self):
100 99
 		rp = mem.get_port()
101 100
 		
102 101
 		comb = [
103  
-			If(self._reg_wc.field.r != 0,
  102
+			If(self._r_wc.field.r != 0,
104 103
 				self.endpoints["sink"].ack.eq(1),
105 104
 				If(self.endpoints["sink"].stb,
106  
-					self._reg_wa.field.we.eq(1),
107  
-					self._reg_wc.field.we.eq(1),
  105
+					self._r_wa.field.we.eq(1),
  106
+					self._r_wc.field.we.eq(1),
108 107
 					wp.we.eq(1)
109 108
 				)
110 109
 			),
111  
-			self._reg_wa.field.w.eq(self._reg_wa.field.r + 1),
112  
-			self._reg_wc.field.w.eq(self._reg_wc.field.r - 1),
  110
+			self._r_wa.field.w.eq(self._r_wa.field.r + 1),
  111
+			self._r_wc.field.w.eq(self._r_wc.field.r - 1),
113 112
 			
114  
-			wp.adr.eq(self._reg_wa.field.r),
  113
+			wp.adr.eq(self._r_wa.field.r),
115 114
 			wp.dat_w.eq(Cat(*self.token("sink").flatten())),
116 115
 			
117  
-			rp.adr.eq(self._reg_ra.field.r),
118  
-			self._reg_rd.field.w.eq(rp.dat_r)
  116
+			rp.adr.eq(self._r_ra.field.r),
  117
+			self._r_rd.field.w.eq(rp.dat_r)
119 118
 		]
120 119
 		
121 120
 		return Fragment(comb, specials={mem})
35  migen/bank/description.py
@@ -2,14 +2,20 @@
2 2
 
3 3
 from migen.fhdl.structure import *
4 4
 from migen.fhdl.specials import Memory
  5
+from migen.fhdl.tracer import get_obj_var_name
5 6
 
6 7
 class _Register(HUID):
7  
-	pass
  8
+	def __init__(self, name):
  9
+		HUID.__init__(self)
  10
+		self.name = get_obj_var_name(name)
  11
+		if self.name is None:
  12
+			raise ValueError("Cannot extract register name from code, need to specify.")
  13
+		if len(self.name) > 2 and self.name[:2] == "r_":
  14
+			self.name = self.name[2:]
8 15
 
9 16
 class RegisterRaw(_Register):
10  
-	def __init__(self, name, size=1):
11  
-		_Register.__init__(self)
12  
-		self.name = name
  17
+	def __init__(self, size=1, name=None):
  18
+		_Register.__init__(self, name)
13 19
 		self.size = size
14 20
 		self.re = Signal()
15 21
 		self.r = Signal(self.size)
@@ -18,8 +24,10 @@ def __init__(self, name, size=1):
18 24
 (READ_ONLY, WRITE_ONLY, READ_WRITE) = range(3)
19 25
 
20 26
 class Field:
21  
-	def __init__(self, name, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, reset=0, atomic_write=False):
22  
-		self.name = name
  27
+	def __init__(self, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, reset=0, atomic_write=False, name=None):
  28
+		self.name = get_obj_var_name(name)
  29
+		if self.name is None:
  30
+			raise ValueError("Cannot extract field name from code, need to specify.")
23 31
 		self.size = size
24 32
 		self.access_bus = access_bus
25 33
 		self.access_dev = access_dev
@@ -35,15 +43,14 @@ def __init__(self, name, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, re
35 43
 				self.we = Signal()
36 44
 
37 45
 class RegisterFields(_Register):
38  
-	def __init__(self, name, fields):
39  
-		_Register.__init__(self)
40  
-		self.name = name
  46
+	def __init__(self, *fields, name=None):
  47
+		_Register.__init__(self, name)
41 48
 		self.fields = fields
42 49
 
43 50
 class RegisterField(RegisterFields):
44  
-	def __init__(self, name, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, reset=0, atomic_write=False):
45  
-		self.field = Field(name, size, access_bus, access_dev, reset, atomic_write)
46  
-		RegisterFields.__init__(self, name, [self.field])
  51
+	def __init__(self, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, reset=0, atomic_write=False, name=None):
  52
+		self.field = Field(size, access_bus, access_dev, reset, atomic_write, name="")
  53
+		RegisterFields.__init__(self, self.field, name=name)
47 54
 
48 55
 def regprefix(prefix, registers):
49 56
 	r = []
@@ -140,7 +147,7 @@ def expand_description(description, busword):
140 147
 							if mode == ALIAS_ATOMIC_HOLD:
141 148
 								commit_list.append(alias)
142 149
 							top -= slice1
143  
-						d.append(RegisterFields(reg.name, f))
  150
+						d.append(RegisterFields(*f, name=reg.name))
144 151
 						alias = FieldAlias(mode, field, top - slice2, top, commit_list)
145 152
 						f = [alias]
146 153
 						if mode == ALIAS_ATOMIC_HOLD:
@@ -150,7 +157,7 @@ def expand_description(description, busword):
150 157
 				else:
151 158
 					f.append(field)
152 159
 			if f:
153  
-				d.append(RegisterFields(reg.name, f))
  160
+				d.append(RegisterFields(*f, name=reg.name))
154 161
 		else:
155 162
 			raise TypeError
156 163
 	return d
7  migen/bank/eventmanager.py
@@ -23,10 +23,9 @@ def do_finalize(self):
23 23
 		sources_u = [v for v in self.__dict__.values() if isinstance(v, _EventSource)]
24 24
 		sources = sorted(sources_u, key=lambda x: x.huid)
25 25
 		n = len(sources)
26  
-		self.status = RegisterRaw("status", n)
27  
-		self.pending = RegisterRaw("pending", n)
28  
-		self.enable = RegisterFields("enable",
29  
-		  [Field("s" + str(i), access_bus=READ_WRITE, access_dev=READ_ONLY) for i in range(n)])
  26
+		self.status = RegisterRaw(n)
  27
+		self.pending = RegisterRaw(n)
  28
+		self.enable = RegisterFields(*(Field(1, READ_WRITE, READ_ONLY, name="e" + str(i)) for i in range(n)))
30 29
 
31 30
 		# status
32 31
 		for i, source in enumerate(sources):
2  migen/bus/csr.py
@@ -68,7 +68,7 @@ def __init__(self, mem_or_size, address, read_only=None, bus=None):
68 68
 			self.word_bits = 0
69 69
 		page_bits = _compute_page_bits(self.mem.depth + self.word_bits)
70 70
 		if page_bits:
71  
-			self._page = RegisterField(self.mem.name_override + "_page", page_bits)
  71
+			self._page = RegisterField(page_bits, name=self.mem.name_override + "_page")
72 72
 		else:
73 73
 			self._page = None
74 74
 		if read_only is None:
23  migen/fhdl/tracer.py
@@ -5,7 +5,8 @@
5 5
 def get_var_name(frame):
6 6
 	code = frame.f_code
7 7
 	call_index = frame.f_lasti
8  
-	if opname[code.co_code[call_index]] != "CALL_FUNCTION":
  8
+	call_opc = opname[code.co_code[call_index]]
  9
+	if call_opc != "CALL_FUNCTION" and call_opc != "CALL_FUNCTION_VAR":
9 10
 		return None
10 11
 	index = call_index+3
11 12
 	while True:
@@ -19,7 +20,7 @@ def get_var_name(frame):
19 20
 		elif opc == "STORE_DEREF":
20 21
 			name_index = int(code.co_code[index+1])
21 22
 			return code.co_cellvars[name_index]
22  
-		elif opc == "LOAD_GLOBAL" or opc == "LOAD_ATTR" or opc == "LOAD_FAST":
  23
+		elif opc == "LOAD_GLOBAL" or opc == "LOAD_ATTR" or opc == "LOAD_FAST" or opc == "LOAD_DEREF":
23 24
 			index += 3
24 25
 		elif opc == "DUP_TOP":
25 26
 			index += 1
@@ -33,6 +34,24 @@ def remove_underscore(s):
33 34
 		s = s[1:]
34 35
 	return s
35 36
 
  37
+def get_obj_var_name(override=None, default=None):
  38
+	if override:
  39
+		return override
  40
+
  41
+	frame = inspect.currentframe().f_back
  42
+	# We can be called via derived classes. Go back the stack frames
  43
+	# until we reach the first class that does not inherit from us.
  44
+	ourclass = frame.f_locals["self"].__class__
  45
+	while "self" in frame.f_locals and isinstance(frame.f_locals["self"], ourclass):
  46
+		frame = frame.f_back
  47
+
  48
+	vn = get_var_name(frame)
  49
+	if vn is None:
  50
+		vn = default
  51
+	else:
  52
+		vn = remove_underscore(vn)
  53
+	return vn
  54
+
36 55
 name_to_idx = defaultdict(int)
37 56
 classname_to_objs = dict()
38 57
 
20  migen/flow/isd.py
@@ -11,11 +11,11 @@ def __init__(self, endpoint, nbits):
11 11
 		self.reset = Signal()
12 12
 		self.freeze = Signal()
13 13
 		
14  
-		self._ack_count = RegisterField("ack_count", self.nbits, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
15  
-		self._nack_count = RegisterField("nack_count", self.nbits, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
16  
-		self._cur_stb = Field("cur_stb", 1, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
17  
-		self._cur_ack = Field("cur_ack", 1, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
18  
-		self._cur_status = RegisterFields("cur_status", [self._cur_stb, self._cur_ack])
  14
+		self._ack_count = RegisterField(self.nbits, READ_ONLY, WRITE_ONLY)
  15
+		self._nack_count = RegisterField(self.nbits, READ_ONLY, WRITE_ONLY)
  16
+		self._cur_stb = Field(1, READ_ONLY, WRITE_ONLY)
  17
+		self._cur_ack = Field(1, READ_ONLY, WRITE_ONLY)
  18
+		self._cur_status = RegisterFields(self._cur_stb, self._cur_ack)
19 19
 	
20 20
 	def get_registers(self):
21 21
 		return [self._ack_count, self._nack_count, self._cur_status]
@@ -57,11 +57,11 @@ class DFGReporter(DFGHook):
57 57
 	def __init__(self, dfg, nbits):
58 58
 		self._nbits = nbits
59 59
 		
60  
-		self._r_magic = RegisterField("magic", 16, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
61  
-		self._r_neps = RegisterField("neps", 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
62  
-		self._r_nbits = RegisterField("nbits", 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
63  
-		self._r_freeze = RegisterField("freeze", 1)
64  
-		self._r_reset = RegisterRaw("reset", 1)
  60
+		self._r_magic = RegisterField(16, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
  61
+		self._r_neps = RegisterField(8, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
  62
+		self._r_nbits = RegisterField(8, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
  63
+		self._r_freeze = RegisterField()
  64
+		self._r_reset = RegisterRaw()
65 65
 		
66 66
 		self.order = []
67 67
 		DFGHook.__init__(self, dfg, self._create)

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