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2  doc/simulation.rst
Source Rendered
@@ -36,8 +36,8 @@ Creating a simulator object
36 36
 The constructor of the ``Simulator`` object takes the following parameters:
37 37
 
38 38
 #. The fragment to simulate. The fragment can (and generally does) contain both synthesizable code and a non-synthesizable list of simulation functions.
39  
-#. A simulator runner object (see :ref:`simrunner`).
40 39
 #. A top-level object (see :ref:`toplevel`). With the default value of ``None``, the simulator creates a default top-level object itself.
  40
+#. A simulator runner object (see :ref:`simrunner`). With the default value of ``None``, Icarus Verilog is used with the default parameters.
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 #. The name of the UNIX domain socket used to communicate with the external simulator through the VPI plug-in (default: "simsocket").
42 42
 #. Additional keyword arguments (if any) are passed to the Verilog conversion function.
43 43
 
5  examples/dataflow/dma.py
@@ -6,7 +6,6 @@
6 6
 from migen.actorlib.sim import *
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 from migen.bus import wishbone, asmibus
8 8
 from migen.sim.generic import Simulator
9  
-from migen.sim.icarus import Runner
10 9
 
11 10
 class MyModel:
12 11
 	def read(self, address):
@@ -51,7 +50,7 @@ def _end_simulation(s):
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 		+ tap.get_fragment() \
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 		+ interconnect.get_fragment() \
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 		+ Fragment(sim=[_end_simulation])
54  
-	sim = Simulator(fragment, Runner())
  53
+	sim = Simulator(fragment)
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 	sim.run()
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57 56
 def asmi_sim(efragment, hub, end_simulation):
@@ -65,7 +64,7 @@ def _end_simulation(s):
65 64
 		+ peripheral.get_fragment() \
66 65
 		+ tap.get_fragment() \
67 66
 		+ Fragment(sim=[_end_simulation])
68  
-	sim = Simulator(fragment, Runner())
  67
+	sim = Simulator(fragment)
69 68
 	sim.run()
70 69
 
71 70
 def test_wb_reader():
3  examples/dataflow/misc.py
@@ -3,7 +3,6 @@
3 3
 from migen.actorlib import misc
4 4
 from migen.actorlib.sim import *
5 5
 from migen.sim.generic import Simulator
6  
-from migen.sim.icarus import Runner
7 6
 
8 7
 def source_gen():
9 8
 	for i in range(10):
@@ -26,7 +25,7 @@ def main():
26 25
 	g.add_connection(loop, sink)
27 26
 	comp = CompositeActor(g)
28 27
 	fragment = comp.get_fragment()
29  
-	sim = Simulator(fragment, Runner())
  28
+	sim = Simulator(fragment)
30 29
 	sim.run(500)
31 30
 
32 31
 main()
3  examples/dataflow/structuring.py
@@ -8,7 +8,6 @@
8 8
 from migen.actorlib import structuring
9 9
 from migen.actorlib.sim import *
10 10
 from migen.sim.generic import Simulator
11  
-from migen.sim.icarus import Runner
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 from migen.flow import perftools
13 12
 
14 13
 pack_factor = 5
@@ -47,7 +46,7 @@ def main():
47 46
 	reporter = perftools.DFGReporter(g)
48 47
 	
49 48
 	fragment = comp.get_fragment() + reporter.get_fragment()
50  
-	sim = Simulator(fragment, Runner())
  49
+	sim = Simulator(fragment)
51 50
 	sim.run(1000)
52 51
 	
53 52
 	g_layout = nx.spectral_layout(g)
3  examples/pytholite/basic.py
@@ -3,7 +3,6 @@
3 3
 from migen.actorlib.sim import *
4 4
 from migen.pytholite.compiler import make_pytholite
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 from migen.sim.generic import Simulator
6  
-from migen.sim.icarus import Runner
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 from migen.fhdl import verilog
8 7
 
9 8
 layout = [("r", 32)]
@@ -19,7 +18,7 @@ def run_sim(ng):
19 18
 	
20 19
 	c = CompositeActor(g)
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 	fragment = c.get_fragment()
22  
-	sim = Simulator(fragment, Runner())
  21
+	sim = Simulator(fragment)
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 	sim.run(30)
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 	del sim
25 24
 
3  examples/pytholite/uio.py
@@ -7,7 +7,6 @@
7 7
 from migen.pytholite.transel import Register
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 from migen.pytholite.compiler import make_pytholite
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 from migen.sim.generic import Simulator
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-from migen.sim.icarus import Runner
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 from migen.fhdl import verilog
12 11
 
13 12
 layout = [("r", 32)]
@@ -40,7 +39,7 @@ def run_sim(ng):
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 	c = CompositeActor(g)
41 40
 	fragment = slave.get_fragment() + intercon.get_fragment() + c.get_fragment()
42 41
 	
43  
-	sim = Simulator(fragment, Runner())
  42
+	sim = Simulator(fragment)
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 	sim.run(50)
45 44
 	del sim
46 45
 
5  examples/sim/abstract_transactions.py
@@ -8,7 +8,6 @@
8 8
 from migen.bus.transactions import *
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 from migen.bus import wishbone, asmibus
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 from migen.sim.generic import Simulator
11  
-from migen.sim.icarus import Runner
12 11
 
13 12
 # Our bus master.
14 13
 # Python generators let us program bus transactions in an elegant sequential style.
@@ -67,7 +66,7 @@ def test_wishbone():
67 66
 	def end_simulation(s):
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 		s.interrupt = master.done
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 	fragment = autofragment.from_local() + Fragment(sim=[end_simulation])
70  
-	sim = Simulator(fragment, Runner())
  69
+	sim = Simulator(fragment)
71 70
 	sim.run()
72 71
 
73 72
 def test_asmi():
@@ -85,7 +84,7 @@ def test_asmi():
85 84
 	def end_simulation(s):
86 85
 		s.interrupt = master.done
87 86
 	fragment = autofragment.from_local() + Fragment(sim=[end_simulation])
88  
-	sim = Simulator(fragment, Runner())
  87
+	sim = Simulator(fragment)
89 88
 	sim.run()
90 89
 	
91 90
 test_wishbone()
6  examples/sim/basic1.py
@@ -3,7 +3,6 @@
3 3
 
4 4
 from migen.fhdl.structure import *
5 5
 from migen.sim.generic import Simulator
6  
-from migen.sim.icarus import Runner
7 6
 
8 7
 # Our simple counter, which increments at every cycle
9 8
 # and prints its current value in simulation.
@@ -31,9 +30,8 @@ def get_fragment(self):
31 30
 
32 31
 def main():
33 32
 	dut = Counter()
34  
-	# Use the Icarus Verilog runner.
35  
-	# We do not specify a top-level object, and use the default.
36  
-	sim = Simulator(dut.get_fragment(), Runner())
  33
+	# We do not specify a top-level nor runner object, and use the defaults.
  34
+	sim = Simulator(dut.get_fragment())
37 35
 	# Since we do not use sim.interrupt, limit the simulation
38 36
 	# to some number of cycles.
39 37
 	sim.run(20)
3  examples/sim/basic2.py
@@ -3,7 +3,6 @@
3 3
 
4 4
 from migen.fhdl.structure import *
5 5
 from migen.sim.generic import Simulator, TopLevel
6  
-from migen.sim.icarus import Runner
7 6
 
8 7
 # A slightly improved counter.
9 8
 # Has a clock enable (CE) signal, counts on more bits
@@ -46,7 +45,7 @@ def main():
46 45
 	dut = Counter()
47 46
 	# Instantiating the generic top-level ourselves lets us
48 47
 	# specify a VCD output file.
49  
-	sim = Simulator(dut.get_fragment(), Runner(), TopLevel("my.vcd"))
  48
+	sim = Simulator(dut.get_fragment(), TopLevel("my.vcd"))
50 49
 	sim.run(20)
51 50
 
52 51
 main()
3  examples/sim/dataflow.py
@@ -4,7 +4,6 @@
4 4
 from migen.flow.network import *
5 5
 from migen.actorlib.sim import *
6 6
 from migen.sim.generic import Simulator
7  
-from migen.sim.icarus import Runner
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9 8
 def source_gen():
10 9
 	for i in range(10):
@@ -26,7 +25,7 @@ def main():
26 25
 	def end_simulation(s):
27 26
 		s.interrupt = source.token_exchanger.done
28 27
 	fragment = comp.get_fragment() + Fragment(sim=[end_simulation])
29  
-	sim = Simulator(fragment, Runner())
  28
+	sim = Simulator(fragment)
30 29
 	sim.run()
31 30
 
32 31
 main()
3  examples/sim/fir.py
@@ -10,7 +10,6 @@
10 10
 from migen.corelogic.misc import optree
11 11
 from migen.fhdl import autofragment
12 12
 from migen.sim.generic import Simulator, PureSimulable
13  
-from migen.sim.icarus import Runner
14 13
 
15 14
 # A synthesizable FIR filter.
16 15
 class FIR:
@@ -63,7 +62,7 @@ def main():
63 62
 	for frequency in [0.05, 0.07, 0.1, 0.15, 0.2]:
64 63
 		tb = TB(fir, frequency)
65 64
 		fragment = autofragment.from_local()
66  
-		sim = Simulator(fragment, Runner())
  65
+		sim = Simulator(fragment)
67 66
 		sim.run(100)
68 67
 		del sim
69 68
 		in_signals += tb.inputs
3  examples/sim/memory.py
@@ -3,7 +3,6 @@
3 3
 
4 4
 from migen.fhdl.structure import *
5 5
 from migen.sim.generic import Simulator
6  
-from migen.sim.icarus import Runner
7 6
 
8 7
 class Mem:
9 8
 	def __init__(self):
@@ -29,7 +28,7 @@ def get_fragment(self):
29 28
 
30 29
 def main():
31 30
 	dut = Mem()
32  
-	sim = Simulator(dut.get_fragment(), Runner())
  31
+	sim = Simulator(dut.get_fragment())
33 32
 	# No need for a cycle limit here, we use sim.interrupt instead.
34 33
 	sim.run()
35 34
 
2  migen/flow/perftools.py
@@ -39,7 +39,7 @@ def on_inactive(self):
39 39
 
40 40
 class DFGReporter(DFGHook):
41 41
 	def __init__(self, dfg):
42  
-		DFGHook.__init__(self, dfg, lambda u, ep, v: EndpointReporter(u.actor.endpoints[ep]))
  42
+		DFGHook.__init__(self, dfg, lambda u, ep, v: EndpointReporter(u.endpoints[ep]))
43 43
 
44 44
 	def get_edge_labels(self):
45 45
 		d = dict()
13  migen/sim/generic.py
@@ -4,6 +4,7 @@
4 4
 from migen.fhdl.structure import *
5 5
 from migen.fhdl import verilog
6 6
 from migen.sim.ipc import *
  7
+from migen.sim import icarus
7 8
 
8 9
 class TopLevel:
9 10
 	def __init__(self, vcd_name=None, vcd_level=1,
@@ -73,13 +74,15 @@ def get(self, sockaddr):
73 74
 		return r
74 75
 
75 76
 class Simulator:
76  
-	def __init__(self, fragment, sim_runner, top_level=None, sockaddr="simsocket", **vopts):
77  
-		self.fragment = fragment
  77
+	def __init__(self, fragment, top_level=None, sim_runner=None, sockaddr="simsocket", **vopts):
78 78
 		if top_level is None:
79  
-			self.top_level = TopLevel()
80  
-		else:
81  
-			self.top_level = top_level
  79
+			top_level = TopLevel()
  80
+		if sim_runner is None:
  81
+			sim_runner = icarus.Runner()		
  82
+		self.fragment = fragment
  83
+		self.top_level = top_level
82 84
 		self.ipc = Initiator(sockaddr)
  85
+		self.sim_runner = sim_runner
83 86
 		
84 87
 		c_top = self.top_level.get(sockaddr)
85 88
 		

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