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2  doc/simulation.rst
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@@ -36,8 +36,8 @@ Creating a simulator object
The constructor of the ``Simulator`` object takes the following parameters:
#. The fragment to simulate. The fragment can (and generally does) contain both synthesizable code and a non-synthesizable list of simulation functions.
-#. A simulator runner object (see :ref:`simrunner`).
#. A top-level object (see :ref:`toplevel`). With the default value of ``None``, the simulator creates a default top-level object itself.
+#. A simulator runner object (see :ref:`simrunner`). With the default value of ``None``, Icarus Verilog is used with the default parameters.
#. The name of the UNIX domain socket used to communicate with the external simulator through the VPI plug-in (default: "simsocket").
#. Additional keyword arguments (if any) are passed to the Verilog conversion function.
5 examples/dataflow/dma.py
View
@@ -6,7 +6,6 @@
from migen.actorlib.sim import *
from migen.bus import wishbone, asmibus
from migen.sim.generic import Simulator
-from migen.sim.icarus import Runner
class MyModel:
def read(self, address):
@@ -51,7 +50,7 @@ def _end_simulation(s):
+ tap.get_fragment() \
+ interconnect.get_fragment() \
+ Fragment(sim=[_end_simulation])
- sim = Simulator(fragment, Runner())
+ sim = Simulator(fragment)
sim.run()
def asmi_sim(efragment, hub, end_simulation):
@@ -65,7 +64,7 @@ def _end_simulation(s):
+ peripheral.get_fragment() \
+ tap.get_fragment() \
+ Fragment(sim=[_end_simulation])
- sim = Simulator(fragment, Runner())
+ sim = Simulator(fragment)
sim.run()
def test_wb_reader():
3  examples/dataflow/misc.py
View
@@ -3,7 +3,6 @@
from migen.actorlib import misc
from migen.actorlib.sim import *
from migen.sim.generic import Simulator
-from migen.sim.icarus import Runner
def source_gen():
for i in range(10):
@@ -26,7 +25,7 @@ def main():
g.add_connection(loop, sink)
comp = CompositeActor(g)
fragment = comp.get_fragment()
- sim = Simulator(fragment, Runner())
+ sim = Simulator(fragment)
sim.run(500)
main()
3  examples/dataflow/structuring.py
View
@@ -8,7 +8,6 @@
from migen.actorlib import structuring
from migen.actorlib.sim import *
from migen.sim.generic import Simulator
-from migen.sim.icarus import Runner
from migen.flow import perftools
pack_factor = 5
@@ -47,7 +46,7 @@ def main():
reporter = perftools.DFGReporter(g)
fragment = comp.get_fragment() + reporter.get_fragment()
- sim = Simulator(fragment, Runner())
+ sim = Simulator(fragment)
sim.run(1000)
g_layout = nx.spectral_layout(g)
3  examples/pytholite/basic.py
View
@@ -3,7 +3,6 @@
from migen.actorlib.sim import *
from migen.pytholite.compiler import make_pytholite
from migen.sim.generic import Simulator
-from migen.sim.icarus import Runner
from migen.fhdl import verilog
layout = [("r", 32)]
@@ -19,7 +18,7 @@ def run_sim(ng):
c = CompositeActor(g)
fragment = c.get_fragment()
- sim = Simulator(fragment, Runner())
+ sim = Simulator(fragment)
sim.run(30)
del sim
3  examples/pytholite/uio.py
View
@@ -7,7 +7,6 @@
from migen.pytholite.transel import Register
from migen.pytholite.compiler import make_pytholite
from migen.sim.generic import Simulator
-from migen.sim.icarus import Runner
from migen.fhdl import verilog
layout = [("r", 32)]
@@ -40,7 +39,7 @@ def run_sim(ng):
c = CompositeActor(g)
fragment = slave.get_fragment() + intercon.get_fragment() + c.get_fragment()
- sim = Simulator(fragment, Runner())
+ sim = Simulator(fragment)
sim.run(50)
del sim
5 examples/sim/abstract_transactions.py
View
@@ -8,7 +8,6 @@
from migen.bus.transactions import *
from migen.bus import wishbone, asmibus
from migen.sim.generic import Simulator
-from migen.sim.icarus import Runner
# Our bus master.
# Python generators let us program bus transactions in an elegant sequential style.
@@ -67,7 +66,7 @@ def test_wishbone():
def end_simulation(s):
s.interrupt = master.done
fragment = autofragment.from_local() + Fragment(sim=[end_simulation])
- sim = Simulator(fragment, Runner())
+ sim = Simulator(fragment)
sim.run()
def test_asmi():
@@ -85,7 +84,7 @@ def test_asmi():
def end_simulation(s):
s.interrupt = master.done
fragment = autofragment.from_local() + Fragment(sim=[end_simulation])
- sim = Simulator(fragment, Runner())
+ sim = Simulator(fragment)
sim.run()
test_wishbone()
6 examples/sim/basic1.py
View
@@ -3,7 +3,6 @@
from migen.fhdl.structure import *
from migen.sim.generic import Simulator
-from migen.sim.icarus import Runner
# Our simple counter, which increments at every cycle
# and prints its current value in simulation.
@@ -31,9 +30,8 @@ def get_fragment(self):
def main():
dut = Counter()
- # Use the Icarus Verilog runner.
- # We do not specify a top-level object, and use the default.
- sim = Simulator(dut.get_fragment(), Runner())
+ # We do not specify a top-level nor runner object, and use the defaults.
+ sim = Simulator(dut.get_fragment())
# Since we do not use sim.interrupt, limit the simulation
# to some number of cycles.
sim.run(20)
3  examples/sim/basic2.py
View
@@ -3,7 +3,6 @@
from migen.fhdl.structure import *
from migen.sim.generic import Simulator, TopLevel
-from migen.sim.icarus import Runner
# A slightly improved counter.
# Has a clock enable (CE) signal, counts on more bits
@@ -46,7 +45,7 @@ def main():
dut = Counter()
# Instantiating the generic top-level ourselves lets us
# specify a VCD output file.
- sim = Simulator(dut.get_fragment(), Runner(), TopLevel("my.vcd"))
+ sim = Simulator(dut.get_fragment(), TopLevel("my.vcd"))
sim.run(20)
main()
3  examples/sim/dataflow.py
View
@@ -4,7 +4,6 @@
from migen.flow.network import *
from migen.actorlib.sim import *
from migen.sim.generic import Simulator
-from migen.sim.icarus import Runner
def source_gen():
for i in range(10):
@@ -26,7 +25,7 @@ def main():
def end_simulation(s):
s.interrupt = source.token_exchanger.done
fragment = comp.get_fragment() + Fragment(sim=[end_simulation])
- sim = Simulator(fragment, Runner())
+ sim = Simulator(fragment)
sim.run()
main()
3  examples/sim/fir.py
View
@@ -10,7 +10,6 @@
from migen.corelogic.misc import optree
from migen.fhdl import autofragment
from migen.sim.generic import Simulator, PureSimulable
-from migen.sim.icarus import Runner
# A synthesizable FIR filter.
class FIR:
@@ -63,7 +62,7 @@ def main():
for frequency in [0.05, 0.07, 0.1, 0.15, 0.2]:
tb = TB(fir, frequency)
fragment = autofragment.from_local()
- sim = Simulator(fragment, Runner())
+ sim = Simulator(fragment)
sim.run(100)
del sim
in_signals += tb.inputs
3  examples/sim/memory.py
View
@@ -3,7 +3,6 @@
from migen.fhdl.structure import *
from migen.sim.generic import Simulator
-from migen.sim.icarus import Runner
class Mem:
def __init__(self):
@@ -29,7 +28,7 @@ def get_fragment(self):
def main():
dut = Mem()
- sim = Simulator(dut.get_fragment(), Runner())
+ sim = Simulator(dut.get_fragment())
# No need for a cycle limit here, we use sim.interrupt instead.
sim.run()
2  migen/flow/perftools.py
View
@@ -39,7 +39,7 @@ def on_inactive(self):
class DFGReporter(DFGHook):
def __init__(self, dfg):
- DFGHook.__init__(self, dfg, lambda u, ep, v: EndpointReporter(u.actor.endpoints[ep]))
+ DFGHook.__init__(self, dfg, lambda u, ep, v: EndpointReporter(u.endpoints[ep]))
def get_edge_labels(self):
d = dict()
13 migen/sim/generic.py
View
@@ -4,6 +4,7 @@
from migen.fhdl.structure import *
from migen.fhdl import verilog
from migen.sim.ipc import *
+from migen.sim import icarus
class TopLevel:
def __init__(self, vcd_name=None, vcd_level=1,
@@ -73,13 +74,15 @@ def get(self, sockaddr):
return r
class Simulator:
- def __init__(self, fragment, sim_runner, top_level=None, sockaddr="simsocket", **vopts):
- self.fragment = fragment
+ def __init__(self, fragment, top_level=None, sim_runner=None, sockaddr="simsocket", **vopts):
if top_level is None:
- self.top_level = TopLevel()
- else:
- self.top_level = top_level
+ top_level = TopLevel()
+ if sim_runner is None:
+ sim_runner = icarus.Runner()
+ self.fragment = fragment
+ self.top_level = top_level
self.ipc = Initiator(sockaddr)
+ self.sim_runner = sim_runner
c_top = self.top_level.get(sockaddr)

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