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34  examples/basic/arrays.py
... ...
@@ -1,25 +1,23 @@
1 1
 from migen.fhdl.structure import *
  2
+from migen.fhdl.module import Module
2 3
 from migen.fhdl import verilog
3 4
 
4  
-dx = 5
5  
-dy = 5
  5
+class Example(Module):
  6
+	def __init__(self):
  7
+		dx = 5
  8
+		dy = 5
6 9
 
7  
-x = Signal(max=dx)
8  
-y = Signal(max=dy)
9  
-out = Signal()
  10
+		x = Signal(max=dx)
  11
+		y = Signal(max=dy)
  12
+		out = Signal()
10 13
 
11  
-my_2d_array = Array(Array(Signal() for a in range(dx)) for b in range(dy))
12  
-comb = [
13  
-	out.eq(my_2d_array[x][y])
14  
-]
  14
+		my_2d_array = Array(Array(Signal() for a in range(dx)) for b in range(dy))
  15
+		self.comb += out.eq(my_2d_array[x][y])
15 16
 
16  
-we = Signal()
17  
-inp = Signal()
18  
-sync = [
19  
-	If(we,
20  
-		my_2d_array[x][y].eq(inp)
21  
-	)
22  
-]
  17
+		we = Signal()
  18
+		inp = Signal()
  19
+		self.sync += If(we,
  20
+				my_2d_array[x][y].eq(inp)
  21
+			)
23 22
 
24  
-f = Fragment(comb, sync)
25  
-print(verilog.convert(f))
  23
+print(verilog.convert(Example()))
27  examples/basic/complex.py
... ...
@@ -1,16 +1,19 @@
  1
+from migen.fhdl.module import Module
1 2
 from migen.genlib.complex import *
2 3
 from migen.fhdl import verilog
3 4
 
4  
-w = Complex(32, 42)
5  
-A = SignalC(16)
6  
-B = SignalC(16)
7  
-Bw = SignalC(16, variable=True)
8  
-C = SignalC(16)
9  
-D = SignalC(16)
10  
-sync = [
11  
-	Bw.eq(B*w),
12  
-	C.eq(A + Bw),
13  
-	D.eq(A - Bw)
14  
-]
  5
+class Example(Module):
  6
+	def __init__(self):
  7
+		w = Complex(32, 42)
  8
+		A = SignalC(16)
  9
+		B = SignalC(16)
  10
+		Bw = SignalC(16, variable=True)
  11
+		C = SignalC(16)
  12
+		D = SignalC(16)
  13
+		self.sync += [
  14
+			Bw.eq(B*w),
  15
+			C.eq(A + Bw),
  16
+			D.eq(A - Bw)
  17
+		]
15 18
 
16  
-print(verilog.convert(Fragment(sync=sync)))
  19
+print(verilog.convert(Example()))
16  examples/basic/fsm.py
... ...
@@ -1,9 +1,15 @@
1 1
 from migen.fhdl.structure import *
  2
+from migen.fhdl.module import Module
2 3
 from migen.fhdl import verilog
3 4
 from migen.genlib.fsm import FSM
4 5
 
5  
-s = Signal()
6  
-myfsm = FSM("FOO", "BAR")
7  
-myfsm.act(myfsm.FOO, s.eq(1), myfsm.next_state(myfsm.BAR))
8  
-myfsm.act(myfsm.BAR, s.eq(0), myfsm.next_state(myfsm.FOO))
9  
-print(verilog.convert(myfsm.get_fragment(), {s}))
  6
+class Example(Module):
  7
+	def __init__(self):
  8
+		self.s = Signal()
  9
+		myfsm = FSM("FOO", "BAR")
  10
+		self.submodules += myfsm
  11
+		myfsm.act(myfsm.FOO, self.s.eq(1), myfsm.next_state(myfsm.BAR))
  12
+		myfsm.act(myfsm.BAR, self.s.eq(0), myfsm.next_state(myfsm.FOO))
  13
+
  14
+example = Example()
  15
+print(verilog.convert(example, {example.s}))
60  examples/basic/lm32_inst.py
... ...
@@ -1,60 +0,0 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.specials import Instance
3  
-from migen.bus import wishbone
4  
-from migen.fhdl import verilog
5  
-
6  
-class LM32:
7  
-	def __init__(self):
8  
-		self.ibus = i = wishbone.Interface()
9  
-		self.dbus = d = wishbone.Interface()
10  
-		self.interrupt = Signal(32)
11  
-		self.ext_break = Signal()
12  
-		self._i_adr_o = Signal(32)
13  
-		self._d_adr_o = Signal(32)
14  
-		self._inst = Instance("lm32_top",
15  
-			Instance.ClockPort("clk_i"),
16  
-			Instance.ResetPort("rst_i"),
17  
-			
18  
-			Instance.Input("interrupt", self.interrupt),
19  
-			#Instance.Input("ext_break", self.ext_break),
20  
-		
21  
-			Instance.Output("I_ADR_O", self._i_adr_o),
22  
-			Instance.Output("I_DAT_O", i.dat_w),
23  
-			Instance.Output("I_SEL_O", i.sel),
24  
-			Instance.Output("I_CYC_O", i.cyc),
25  
-			Instance.Output("I_STB_O", i.stb),
26  
-			Instance.Output("I_WE_O", i.we),
27  
-			Instance.Output("I_CTI_O", i.cti),
28  
-			Instance.Output("I_LOCK_O"),
29  
-			Instance.Output("I_BTE_O", i.bte),
30  
-			Instance.Input("I_DAT_I", i.dat_r),
31  
-			Instance.Input("I_ACK_I", i.ack),
32  
-			Instance.Input("I_ERR_I", i.err),
33  
-			Instance.Input("I_RTY_I", 0),
34  
-			
35  
-			Instance.Output("D_ADR_O", self._d_adr_o),
36  
-			Instance.Output("D_DAT_O", d.dat_w),
37  
-			Instance.Output("D_SEL_O", d.sel),
38  
-			Instance.Output("D_CYC_O", d.cyc),
39  
-			Instance.Output("D_STB_O", d.stb),
40  
-			Instance.Output("D_WE_O", d.we),
41  
-			Instance.Output("D_CTI_O", d.cti),
42  
-			Instance.Output("D_LOCK_O"),
43  
-			Instance.Output("D_BTE_O", d.bte),
44  
-			Instance.Input("D_DAT_I", d.dat_r),
45  
-			Instance.Input("D_ACK_I", d.ack),
46  
-			Instance.Input("D_ERR_I", d.err),
47  
-			Instance.Input("D_RTY_I", 0))
48  
-
49  
-	def get_fragment(self):
50  
-		comb = [
51  
-			self.ibus.adr.eq(self._i_adr_o[2:]),
52  
-			self.dbus.adr.eq(self._d_adr_o[2:])
53  
-		]
54  
-		return Fragment(comb=comb, specials={self._inst})
55  
-
56  
-cpus = [LM32() for i in range(4)]
57  
-frag = Fragment()
58  
-for cpu in cpus:
59  
-	frag += cpu.get_fragment()
60  
-print(verilog.convert(frag, {cpus[0].interrupt}))
17  examples/basic/memory.py
... ...
@@ -1,12 +1,15 @@
1 1
 from migen.fhdl.structure import Fragment
2 2
 from migen.fhdl.specials import Memory
  3
+from migen.fhdl.module import Module
3 4
 from migen.fhdl import verilog
4 5
 
5  
-mem = Memory(32, 100, init=[5, 18, 32])
6  
-p1 = mem.get_port(write_capable=True, we_granularity=8)
7  
-p2 = mem.get_port(has_re=True, clock_domain="rd")
  6
+class Example(Module):
  7
+	def __init__(self):
  8
+		self.specials.mem = Memory(32, 100, init=[5, 18, 32])
  9
+		p1 = self.mem.get_port(write_capable=True, we_granularity=8)
  10
+		p2 = self.mem.get_port(has_re=True, clock_domain="rd")
  11
+		self.ios = {p1.adr, p1.dat_r, p1.we, p1.dat_w,
  12
+			p2.adr, p2.dat_r, p2.re}
8 13
 
9  
-f = Fragment(specials={mem})
10  
-v = verilog.convert(f, ios={p1.adr, p1.dat_r, p1.we, p1.dat_w,
11  
-	p2.adr, p2.dat_r, p2.re})
12  
-print(v)
  14
+example = Example()
  15
+print(verilog.convert(example, example.ios))
26  examples/basic/namer.py
... ...
@@ -1,5 +1,6 @@
1 1
 from migen.fhdl.structure import *
2 2
 from migen.fhdl import verilog
  3
+from migen.fhdl.module import Module
3 4
 from migen.genlib.misc import optree
4 5
 
5 6
 def gen_list(n):
@@ -24,17 +25,18 @@ class Toto:
24 25
 	def __init__(self):
25 26
 		self.sigs = gen_list(2)
26 27
 
27  
-a = [Bar() for x in range(3)]
28  
-b = [Foo() for x in range(3)]
29  
-c = b
30  
-b = [Bar() for x in range(2)]
  28
+class Example(Module):
  29
+	def __init__(self):
  30
+		a = [Bar() for x in range(3)]
  31
+		b = [Foo() for x in range(3)]
  32
+		c = b
  33
+		b = [Bar() for x in range(2)]
31 34
 
32  
-output = Signal()
33  
-allsigs = []
34  
-for lst in [a, b, c]:
35  
-	for obj in lst:
36  
-		allsigs.extend(obj.sigs)
37  
-comb = [output.eq(optree("|", allsigs))]
  35
+		output = Signal()
  36
+		allsigs = []
  37
+		for lst in [a, b, c]:
  38
+			for obj in lst:
  39
+				allsigs.extend(obj.sigs)
  40
+		self.comb += output.eq(optree("|", allsigs))
38 41
 
39  
-f = Fragment(comb)
40  
-print(verilog.convert(f))
  42
+print(verilog.convert(Example()))
3  examples/basic/psync.py
@@ -15,6 +15,5 @@ def lower(dr):
15 15
 		return XilinxMultiRegImpl(dr.i, dr.idomain, dr.o, dr.odomain, dr.n)
16 16
 
17 17
 ps = PulseSynchronizer("from", "to")
18  
-f = ps.get_fragment()
19  
-v = verilog.convert(f, {ps.i, ps.o}, special_overrides={MultiReg: XilinxMultiReg})
  18
+v = verilog.convert(ps, {ps.i, ps.o}, special_overrides={MultiReg: XilinxMultiReg})
20 19
 print(v)
35  examples/basic/simple_gpio.py
... ...
@@ -1,23 +1,30 @@
1 1
 from migen.fhdl.structure import *
  2
+from migen.fhdl.module import Module
2 3
 from migen.fhdl import verilog
  4
+from migen.genlib.cdc import MultiReg
3 5
 from migen.bank import description, csrgen
4 6
 from migen.bank.description import READ_ONLY, WRITE_ONLY
5 7
 
6  
-ninputs = 32
7  
-noutputs = 32
  8
+class Example(Module):
  9
+	def __init__(self, ninputs=32, noutputs=32):
  10
+		r_o = description.RegisterField(noutputs, atomic_write=True)
  11
+		r_i = description.RegisterField(ninputs, READ_ONLY, WRITE_ONLY)
8 12
 
9  
-oreg = description.RegisterField("o", noutputs, atomic_write=True)
10  
-ireg = description.RegisterField("i", ninputs, READ_ONLY, WRITE_ONLY)
  13
+		self.submodules.bank = csrgen.Bank([r_o, r_i])
  14
+		self.gpio_in = Signal(ninputs)
  15
+		self.gpio_out  = Signal(ninputs)
11 16
 
12  
-# input path
13  
-gpio_in = Signal(ninputs)
14  
-gpio_in_s = Signal(ninputs) # synchronizer
15  
-insync = [gpio_in_s.eq(gpio_in), ireg.field.w.eq(gpio_in_s)]
16  
-inf = Fragment(sync=insync)
  17
+		###
17 18
 
18  
-bank = csrgen.Bank([oreg, ireg])
19  
-f = bank.get_fragment() + inf
20  
-oreg.field.r.name_override = "gpio_out"
21  
-i = bank.interface
22  
-v = verilog.convert(f, {i.dat_r, oreg.field.r, i.adr, i.we, i.dat_w, gpio_in})
  19
+		gpio_in_s = Signal(ninputs)
  20
+		self.specials += MultiReg(self.gpio_in, "ext", gpio_in_s, "sys")
  21
+		self.comb += [
  22
+			r_i.field.w.eq(gpio_in_s),
  23
+			self.gpio_out.eq(r_o.field.r)
  24
+		]
  25
+
  26
+example = Example()
  27
+i = example.bank.bus
  28
+v = verilog.convert(example, {i.dat_r, i.adr, i.we, i.dat_w,
  29
+	example.gpio_in, example.gpio_out})
23 30
 print(v)
18  examples/basic/tristate.py
... ...
@@ -1,12 +1,16 @@
1 1
 from migen.fhdl.structure import *
2 2
 from migen.fhdl.specials import Tristate
  3
+from migen.fhdl.module import Module
3 4
 from migen.fhdl import verilog
4 5
 
5  
-n = 6
6  
-pad = Signal(n)
7  
-o = Signal(n)
8  
-oe = Signal()
9  
-i = Signal(n)
  6
+class Example(Module):
  7
+	def __init__(self, n=6):
  8
+		self.pad = Signal(n)
  9
+		self.o = Signal(n)
  10
+		self.oe = Signal()
  11
+		self.i = Signal(n)
10 12
 
11  
-f = Fragment(specials={Tristate(pad, o, oe, i)})
12  
-print(verilog.convert(f, ios={pad, o, oe, i}))
  13
+		self.specials += Tristate(self.pad, self.o, self.oe, self.i)
  14
+
  15
+e = Example()
  16
+print(verilog.convert(e, ios={e.pad, e.o, e.oe, e.i}))
19  examples/basic/two_dividers.py
... ...
@@ -1,10 +1,15 @@
1 1
 from migen.fhdl import verilog
  2
+from migen.fhdl.module import Module
2 3
 from migen.genlib import divider
3 4
 
4  
-d1 = divider.Divider(16)
5  
-d2 = divider.Divider(16)
6  
-frag = d1.get_fragment() + d2.get_fragment()
7  
-o = verilog.convert(frag, {
8  
-	d1.ready_o, d1.quotient_o, d1.remainder_o, d1.start_i, d1.dividend_i, d1.divisor_i,
9  
-	d2.ready_o, d2.quotient_o, d2.remainder_o, d2.start_i, d2.dividend_i, d2.divisor_i})
10  
-print(o)
  5
+class Example(Module):
  6
+	def __init__(self):
  7
+		d1 = divider.Divider(16)
  8
+		d2 = divider.Divider(16)
  9
+		self.submodules += d1, d2
  10
+		self.ios = {
  11
+			d1.ready_o, d1.quotient_o, d1.remainder_o, d1.start_i, d1.dividend_i, d1.divisor_i,
  12
+			d2.ready_o, d2.quotient_o, d2.remainder_o, d2.start_i, d2.dividend_i, d2.divisor_i}
  13
+
  14
+example = Example()
  15
+print(verilog.convert(example, example.ios))
5  examples/pytholite/basic.py
@@ -17,8 +17,7 @@ def run_sim(ng):
17 17
 	g.add_connection(ng, d)
18 18
 	
19 19
 	c = CompositeActor(g)
20  
-	fragment = c.get_fragment()
21  
-	sim = Simulator(fragment)
  20
+	sim = Simulator(c)
22 21
 	sim.run(30)
23 22
 	del sim
24 23
 
@@ -32,6 +31,6 @@ def main():
32 31
 	run_sim(ng_pytholite)
33 32
 	
34 33
 	print("Converting Pytholite to Verilog:")
35  
-	print(verilog.convert(ng_pytholite.get_fragment()))
  34
+	print(verilog.convert(ng_pytholite))
36 35
 
37 36
 main()
23  examples/pytholite/uio.py
@@ -7,6 +7,7 @@
7 7
 from migen.pytholite.transel import Register
8 8
 from migen.pytholite.compiler import make_pytholite
9 9
 from migen.sim.generic import Simulator
  10
+from migen.fhdl.module import Module
10 11
 from migen.fhdl.specials import Memory
11 12
 from migen.fhdl import verilog
12 13
 
@@ -29,18 +30,18 @@ class SlaveModel(wishbone.TargetModel):
29 30
 	def read(self, address):
30 31
 		return address + 4
31 32
 
  33
+class TestBench(Module):
  34
+	def __init__(self, ng):
  35
+		g = DataFlowGraph()
  36
+		d = Dumper(layout)
  37
+		g.add_connection(ng, d)
  38
+		
  39
+		self.submodules.slave = wishbone.Target(SlaveModel())
  40
+		self.submodules.intercon = wishbone.InterconnectPointToPoint(ng.buses["wb"], self.slave.bus)
  41
+		self.submodules.ca = CompositeActor(g)
  42
+
32 43
 def run_sim(ng):
33  
-	g = DataFlowGraph()
34  
-	d = Dumper(layout)
35  
-	g.add_connection(ng, d)
36  
-	
37  
-	slave = wishbone.Target(SlaveModel())
38  
-	intercon = wishbone.InterconnectPointToPoint(ng.buses["wb"], slave.bus)
39  
-	
40  
-	c = CompositeActor(g)
41  
-	fragment = slave.get_fragment() + intercon.get_fragment() + c.get_fragment()
42  
-	
43  
-	sim = Simulator(fragment)
  44
+	sim = Simulator(TestBench(ng))
44 45
 	sim.run(50)
45 46
 	del sim
46 47
 
2  migen/fhdl/verilog.py
@@ -260,6 +260,8 @@ def convert(f, ios=None, name="top",
260 260
   return_ns=False,
261 261
   special_overrides=dict(),
262 262
   display_run=False):
  263
+	if not isinstance(f, Fragment):
  264
+		f = f.get_fragment()
263 265
 	if ios is None:
264 266
 		ios = set()
265 267
 	if clock_domains is None:
2  migen/sim/generic.py
@@ -76,6 +76,8 @@ def get(self, sockaddr):
76 76
 
77 77
 class Simulator:
78 78
 	def __init__(self, fragment, top_level=None, sim_runner=None, sockaddr="simsocket", **vopts):
  79
+		if not isinstance(fragment, Fragment):
  80
+			fragment = fragment.get_fragment()
79 81
 		if top_level is None:
80 82
 			top_level = TopLevel()
81 83
 		if sim_runner is None:
3  vpi/Makefile
... ...
@@ -1,6 +1,5 @@
1  
-CC=clang
2 1
 INSTDIR=/usr/lib/ivl
3  
-INCDIRS=
  2
+INCDIRS=-I/usr/include/iverilog
4 3
 
5 4
 OBJ=ipc.o main.o
6 5
 

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