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  • 3 commits
  • 3 files changed
  • 0 commit comments
  • 1 contributor
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13 migen/bus/simple.py
@@ -1,5 +1,12 @@
from migen.fhdl import structure as f
+def GetSigName(signal, slave):
+ if signal[0] ^ slave:
+ suffix = "_o"
+ else:
+ suffix = "_i"
+ return signal[1] + suffix
+
# desc is a list of tuples, each made up of:
# 0) boolean: "master to slave"
# 1) string: name
@@ -7,13 +14,9 @@
class Simple():
def __init__(self, desc, slave, name):
for signal in desc:
- if signal[0] ^ slave:
- suffix = "_o"
- else:
- suffix = "_i"
modules = self.__module__.split('.')
busname = modules[len(modules)-1]
if name:
busname += "_" + name
- signame = signal[1]+suffix
+ signame = GetSigName(signal, slave)
setattr(self, signame, f.Signal(f.BV(signal[2]), busname + "_" + signame))
View
13 migen/corelogic/multimux.py
@@ -0,0 +1,13 @@
+from migen.fhdl import structure as f
+
+def MultiMux(sel, inputs, output):
+ n = len(inputs)
+ i = 0
+ comb = []
+ for osig in output:
+ choices = [x[i] for x in inputs]
+ cases = [(f.Constant(j, sel.bv), [f.Assign(osig, choices[j])]) for j in range(n)]
+ default = cases.pop()[1]
+ comb.append(f.Case(sel, cases, default))
+ i += 1
+ return comb
View
4 migen/fhdl/verilog.py
@@ -65,6 +65,10 @@ def _printnode(ns, level, comb, node):
r += "\t"*(level + 1) + _printexpr(ns, case[0]) + ": begin\n"
r += _printnode(ns, level + 2, comb, case[1])
r += "\t"*(level + 1) + "end\n"
+ if node.default.l:
+ r += "\t"*(level + 1) + "default: begin\n"
+ r += _printnode(ns, level + 2, comb, node.default)
+ r += "\t"*(level + 1) + "end\n"
r += "\t"*level + "endcase\n"
return r
else:

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