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  • 3 commits
  • 3 files changed
  • 0 commit comments
  • 1 contributor
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5 migen/bank/description.py
@@ -5,6 +5,11 @@ def regprefix(prefix, registers):
register.name = prefix + register.name
return registers
+def memprefix(prefix, memories):
+ for memory in memories:
+ memory.name_override = prefix + memory.name_override
+ return memories
+
class RegisterRaw:
def __init__(self, name, size=1):
self.name = name
View
5 migen/fhdl/specials.py
@@ -180,12 +180,13 @@ def __init__(self, adr, dat_r, we=None, dat_w=None,
self.clock_domain = clock_domain
class Memory(Special):
- def __init__(self, width, depth, init=None):
+ def __init__(self, width, depth, init=None, name="mem"):
Special.__init__(self)
self.width = width
self.depth = depth
self.ports = []
self.init = init
+ self.name_override = name
def get_port(self, write_capable=False, async_read=False,
has_re=False, we_granularity=0, mode=WRITE_FIRST,
@@ -234,8 +235,6 @@ def add(*sigs):
add(p.dat_r)
return s
- name_override = "mem"
-
@staticmethod
def emit_verilog(memory, ns, clock_domains):
r = ""
View
2  migen/uio/ioo.py
@@ -15,7 +15,7 @@ def __init__(self, dataflow=None, buses={}):
self._memories = set(v for v in self.buses.values() if isinstance(v, Memory))
def get_fragment(self):
- return Fragment(specials={self._memories})
+ return Fragment(specials=self._memories)
(_WAIT_COMPLETE, _WAIT_POLL) = range(2)

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