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  • 4 commits
  • 4 files changed
  • 0 commit comments
  • 1 contributor
View
28 migen/actorlib/spi.py
@@ -20,34 +20,6 @@ def _convert_layout(layout):
r.append((element[0], element[1]))
return r
-def _create_csrs_assign(layout, target, atomic, prefix=""):
- csrs = []
- assigns = []
- for element in layout:
- if isinstance(element[1], list):
- r_csrs, r_assigns = _create_csrs_assign(element[1],
- atomic,
- getattr(target, element[0]),
- element[0] + "_")
- csrs += r_csrs
- assigns += r_assigns
- else:
- name = element[0]
- nbits = element[1]
- if len(element) > 2:
- reset = element[2]
- else:
- reset = 0
- if len(element) > 3:
- alignment = element[3]
- else:
- alignment = 0
- reg = CSRStorage(nbits + alignment, reset=reset, atomic_write=atomic,
- alignment_bits=alignment, name=prefix + name)
- csrs.append(reg)
- assigns.append(getattr(target, name).eq(reg.storage))
- return csrs, assigns
-
(MODE_EXTERNAL, MODE_SINGLE_SHOT, MODE_CONTINUOUS) = range(3)
class SingleGenerator(Module, AutoCSR):
View
30 migen/bus/csr.py
@@ -25,25 +25,33 @@ def __init__(self, generator, bus=None):
bus = Interface()
self.bus = bus
self.transaction = None
+ self.read_data_ready = False
self.done = False
def do_simulation(self, s):
if not self.done:
if self.transaction is not None:
if isinstance(self.transaction, TRead):
- self.transaction.data = s.rd(self.bus.dat_r)
+ if self.read_data_ready:
+ self.transaction.data = s.rd(self.bus.dat_r)
+ self.transaction = None
+ self.read_data_ready = False
+ else:
+ self.read_data_ready = True
else:
s.wr(self.bus.we, 0)
- try:
- self.transaction = next(self.generator)
- except StopIteration:
- self.transaction = None
- self.done = True
- if self.transaction is not None:
- s.wr(self.bus.adr, self.transaction.address)
- if isinstance(self.transaction, TWrite):
- s.wr(self.bus.we, 1)
- s.wr(self.bus.dat_w, self.transaction.data)
+ self.transaction = None
+ if self.transaction is None:
+ try:
+ self.transaction = next(self.generator)
+ except StopIteration:
+ self.transaction = None
+ self.done = True
+ if self.transaction is not None:
+ s.wr(self.bus.adr, self.transaction.address)
+ if isinstance(self.transaction, TWrite):
+ s.wr(self.bus.we, 1)
+ s.wr(self.bus.dat_w, self.transaction.data)
class SRAM(Module):
def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
View
8 migen/pytholite/expr.py
@@ -11,6 +11,14 @@ def __init__(self, symdict):
self.symdict = symdict
def visit_expr(self, node):
+ # Attempt compile-time evaluation first
+ try:
+ result = eval_ast(node, self.symdict)
+ except:
+ result = None
+ if isinstance(result, int):
+ return result
+
if isinstance(node, ast.Call):
return self.visit_expr_call(node)
elif isinstance(node, ast.BinOp):
View
4 migen/pytholite/io.py
@@ -101,7 +101,7 @@ def _gen_wishbone_io(compiler, modelname, model, to_model, from_model, bus):
]
sel = to_model["sel"]
if isinstance(sel, ast.Name) and sel.id == "None":
- nbytes = (len(bus.dat_w) + 7)//8
+ nbytes = (flen(bus.dat_w) + 7)//8
state.append(bus.sel.eq(2**nbytes-1))
else:
state.append(bus.sel.eq(compiler.ec.visit_expr(sel)))
@@ -121,7 +121,7 @@ def _gen_memory_io(compiler, modelname, model, to_model, from_model, port):
s1.append(port.dat_w.eq(compiler.ec.visit_expr(to_model["data"])))
sel = to_model["sel"]
if isinstance(sel, ast.Name) and sel.id == "None":
- nbytes = (len(port.dat_w) + 7)//8
+ nbytes = (flen(port.dat_w) + 7)//8
s1.append(port.we.eq(2**nbytes-1))
else:
s1.append(port.we.eq(compiler.ec.visit_expr(sel)))

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