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28  migen/actorlib/spi.py
@@ -20,34 +20,6 @@ def _convert_layout(layout):
20 20
 			r.append((element[0], element[1]))
21 21
 	return r
22 22
 
23  
-def _create_csrs_assign(layout, target, atomic, prefix=""):
24  
-	csrs = []
25  
-	assigns = []
26  
-	for element in layout:
27  
-		if isinstance(element[1], list):
28  
-			r_csrs, r_assigns = _create_csrs_assign(element[1],
29  
-				atomic,
30  
-				getattr(target, element[0]),
31  
-				element[0] + "_")
32  
-			csrs += r_csrs
33  
-			assigns += r_assigns
34  
-		else:
35  
-			name = element[0]
36  
-			nbits = element[1]
37  
-			if len(element) > 2:
38  
-				reset = element[2]
39  
-			else:
40  
-				reset = 0
41  
-			if len(element) > 3:
42  
-				alignment = element[3]
43  
-			else:
44  
-				alignment = 0
45  
-			reg = CSRStorage(nbits + alignment, reset=reset, atomic_write=atomic,
46  
-				alignment_bits=alignment, name=prefix + name)
47  
-			csrs.append(reg)
48  
-			assigns.append(getattr(target, name).eq(reg.storage))
49  
-	return csrs, assigns
50  
-
51 23
 (MODE_EXTERNAL, MODE_SINGLE_SHOT, MODE_CONTINUOUS) = range(3)
52 24
 
53 25
 class SingleGenerator(Module, AutoCSR):
30  migen/bus/csr.py
@@ -25,25 +25,33 @@ def __init__(self, generator, bus=None):
25 25
 			bus = Interface()
26 26
 		self.bus = bus
27 27
 		self.transaction = None
  28
+		self.read_data_ready = False
28 29
 		self.done = False
29 30
 		
30 31
 	def do_simulation(self, s):
31 32
 		if not self.done:
32 33
 			if self.transaction is not None:
33 34
 				if isinstance(self.transaction, TRead):
34  
-					self.transaction.data = s.rd(self.bus.dat_r)
  35
+					if self.read_data_ready:
  36
+						self.transaction.data = s.rd(self.bus.dat_r)
  37
+						self.transaction = None
  38
+						self.read_data_ready = False
  39
+					else:
  40
+						self.read_data_ready = True
35 41
 				else:
36 42
 					s.wr(self.bus.we, 0)
37  
-			try:
38  
-				self.transaction = next(self.generator)
39  
-			except StopIteration:
40  
-				self.transaction = None
41  
-				self.done = True
42  
-			if self.transaction is not None:
43  
-				s.wr(self.bus.adr, self.transaction.address)
44  
-				if isinstance(self.transaction, TWrite):
45  
-					s.wr(self.bus.we, 1)
46  
-					s.wr(self.bus.dat_w, self.transaction.data)
  43
+					self.transaction = None
  44
+			if self.transaction is None:
  45
+				try:
  46
+					self.transaction = next(self.generator)
  47
+				except StopIteration:
  48
+					self.transaction = None
  49
+					self.done = True
  50
+				if self.transaction is not None:
  51
+					s.wr(self.bus.adr, self.transaction.address)
  52
+					if isinstance(self.transaction, TWrite):
  53
+						s.wr(self.bus.we, 1)
  54
+						s.wr(self.bus.dat_w, self.transaction.data)
47 55
 
48 56
 class SRAM(Module):
49 57
 	def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
8  migen/pytholite/expr.py
@@ -11,6 +11,14 @@ def __init__(self, symdict):
11 11
 		self.symdict = symdict
12 12
 	
13 13
 	def visit_expr(self, node):
  14
+		# Attempt compile-time evaluation first
  15
+		try:
  16
+			result = eval_ast(node, self.symdict)
  17
+		except:
  18
+			result = None
  19
+		if isinstance(result, int):
  20
+			return result
  21
+
14 22
 		if isinstance(node, ast.Call):
15 23
 			return self.visit_expr_call(node)
16 24
 		elif isinstance(node, ast.BinOp):
4  migen/pytholite/io.py
@@ -101,7 +101,7 @@ def _gen_wishbone_io(compiler, modelname, model, to_model, from_model, bus):
101 101
 		]
102 102
 		sel = to_model["sel"]
103 103
 		if isinstance(sel, ast.Name) and sel.id == "None":
104  
-			nbytes = (len(bus.dat_w) + 7)//8
  104
+			nbytes = (flen(bus.dat_w) + 7)//8
105 105
 			state.append(bus.sel.eq(2**nbytes-1))
106 106
 		else:
107 107
 			state.append(bus.sel.eq(compiler.ec.visit_expr(sel)))
@@ -121,7 +121,7 @@ def _gen_memory_io(compiler, modelname, model, to_model, from_model, port):
121 121
 		s1.append(port.dat_w.eq(compiler.ec.visit_expr(to_model["data"])))
122 122
 		sel = to_model["sel"]
123 123
 		if isinstance(sel, ast.Name) and sel.id == "None":
124  
-			nbytes = (len(port.dat_w) + 7)//8
  124
+			nbytes = (flen(port.dat_w) + 7)//8
125 125
 			s1.append(port.we.eq(2**nbytes-1))
126 126
 		else:
127 127
 			s1.append(port.we.eq(compiler.ec.visit_expr(sel)))

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