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18  migen/bus/lasmibus.py
@@ -66,13 +66,23 @@ def __init__(self, controllers, nmasters, cba_shift):
66 66
 				controller_selected = [1]*nmasters
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 			master_req_acks = [0]*nmasters
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 			master_dat_acks = [0]*nmasters
69  
-			for nb in range(nbanks):
  69
+			rrs = [roundrobin.RoundRobin(nmasters, roundrobin.SP_CE) for n in range(nbanks)]
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+			self.submodules += rrs
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+			for nb, rr in enumerate(rrs):
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 				bank = getattr(controller, "bank"+str(nb))
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+				# for each master, determine if another bank locks it
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+				master_locked = []
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+				for nm, master in enumerate(self.masters):
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+					locked = 0
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+					for other_nb, other_rr in enumerate(rrs):
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+						if other_nb != nb:
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+							other_bank = getattr(controller, "bank"+str(other_nb))
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+							locked = locked | (other_bank.lock & (other_rr.grant == nm))
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+					master_locked.append(locked)
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+
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 				# arbitrate
73  
-				rr = roundrobin.RoundRobin(nmasters, roundrobin.SP_CE)
74  
-				self.submodules += rr
75  
-				bank_selected = [cs & (ba == nb) for cs, ba in zip(controller_selected, m_ba)]
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+				bank_selected = [cs & (ba == nb) & ~locked for cs, ba, locked in zip(controller_selected, m_ba, master_locked)]
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 				bank_requested = [bs & master.stb for bs, master in zip(bank_selected, self.masters)]
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 				self.comb += [
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 					rr.request.eq(Cat(*bank_requested)),
25  migen/genlib/fifo.py
@@ -129,3 +129,28 @@ def __init__(self, width_or_layout, depth):
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 			rdport.adr.eq(consume.q_binary[:-1]),
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 			self.dout_bits.eq(rdport.dat_r)
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 		]
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+
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+class _SyncFIFOTB(Module):
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+	def __init__(self):
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+		self.submodules.dut = SyncFIFO([("a", 32), ("b", 32)], 2)
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+
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+		self.sync += [
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+			If(self.dut.we & self.dut.writable, 
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+				self.dut.din.a.eq(self.dut.din.a + 1),
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+				self.dut.din.b.eq(self.dut.din.b + 2)
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+			)
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+		]
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+		
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+	def do_simulation(self, s):
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+		s.wr(self.dut.we, s.cycle_counter % 4 == 0)
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+		s.wr(self.dut.re, s.cycle_counter % 3 == 0)
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+		print("readable: {0} re: {1} data: {2}/{3}".format(s.rd(self.dut.readable),
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+			s.rd(self.dut.re),
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+			s.rd(self.dut.dout.a), s.rd(self.dut.dout.b)))
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+
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+def _main():
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+	from migen.sim.generic import Simulator
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+	Simulator(_SyncFIFOTB()).run(20)
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+
  155
+if __name__ == "__main__":
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+	_main()

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