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20  migen/fhdl/verilog.py
@@ -230,7 +230,7 @@ def _call_special_classmethod(overrides, obj, method, *args, **kwargs):
230 230
 	else:
231 231
 		return None
232 232
 
233  
-def _lower_specials(overrides, specials):
  233
+def _lower_specials_step(overrides, specials):
234 234
 	f = Fragment()
235 235
 	lowered_specials = set()
236 236
 	for special in sorted(specials, key=lambda x: x.huid):
@@ -240,6 +240,24 @@ def _lower_specials(overrides, specials):
240 240
 			lowered_specials.add(special)
241 241
 	return f, lowered_specials
242 242
 
  243
+def _can_lower(overrides, specials):
  244
+	for special in specials:
  245
+		cl = special.__class__
  246
+		if cl in overrides:
  247
+			cl = overrides[cl]
  248
+		if hasattr(cl, "lower"):
  249
+			return True
  250
+	return False
  251
+
  252
+def _lower_specials(overrides, specials):
  253
+	f, lowered_specials = _lower_specials_step(overrides, specials)
  254
+	while _can_lower(overrides, f.specials):
  255
+		f2, lowered_specials2 = _lower_specials_step(overrides, f.specials)
  256
+		f += f2
  257
+		lowered_specials |= lowered_specials2
  258
+		f.specials -= lowered_specials2
  259
+	return f, lowered_specials
  260
+
243 261
 def _printspecials(overrides, specials, ns):
244 262
 	r = ""
245 263
 	for special in sorted(specials, key=lambda x: x.huid):
25  migen/genlib/cdc.py
@@ -3,7 +3,17 @@
3 3
 from migen.fhdl.specials import Special
4 4
 from migen.fhdl.tools import list_signals
5 5
 
6  
-class MultiRegImpl:
  6
+class NoRetiming(Special):
  7
+	def __init__(self, reg):
  8
+		Special.__init__(self)
  9
+		self.reg = reg
  10
+
  11
+	# do nothing
  12
+	@staticmethod
  13
+	def lower(dr):
  14
+		return Module()
  15
+
  16
+class MultiRegImpl(Module):
7 17
 	def __init__(self, i, o, odomain, n):
8 18
 		self.i = i
9 19
 		self.o = o
@@ -12,16 +22,15 @@ def __init__(self, i, o, odomain, n):
12 22
 		w, signed = value_bits_sign(self.i)
13 23
 		self.regs = [Signal((w, signed)) for i in range(n)]
14 24
 
15  
-	def get_fragment(self):
  25
+		###
  26
+	
16 27
 		src = self.i
17  
-		o_sync = []
18 28
 		for reg in self.regs:
19  
-			o_sync.append(reg.eq(src))
  29
+			sd = getattr(self.sync, self.odomain)
  30
+			sd += reg.eq(src)
20 31
 			src = reg
21  
-		comb = [
22  
-			self.o.eq(src)
23  
-		]
24  
-		return Fragment(comb, {self.odomain: o_sync})
  32
+		self.comb += self.o.eq(src)
  33
+		self.specials += [NoRetiming(reg) for reg in self.regs]
25 34
 
26 35
 class MultiReg(Special):
27 36
 	def __init__(self, i, o, odomain="sys", n=2):
14  migen/genlib/fifo.py
... ...
@@ -1,7 +1,7 @@
1 1
 from migen.fhdl.structure import *
2 2
 from migen.fhdl.specials import Memory
3 3
 from migen.fhdl.module import Module
4  
-from migen.genlib.cdc import MultiReg, GrayCounter
  4
+from migen.genlib.cdc import NoRetiming, MultiReg, GrayCounter
5 5
 
6 6
 def _inc(signal, modulo):
7 7
 	if modulo == 2**len(signal):
@@ -85,12 +85,16 @@ def __init__(self, width, depth):
85 85
 			consume.ce.eq(self.readable & self.re)
86 86
 		]
87 87
 
88  
-		# TODO: disable retiming on produce.q and consume.q
89  
-
90 88
 		produce_rdomain = Signal(depth_bits+1)
91  
-		self.specials += MultiReg(produce.q, produce_rdomain, "read")
  89
+		self.specials += [
  90
+			NoRetiming(produce.q),
  91
+			MultiReg(produce.q, produce_rdomain, "read")
  92
+		]
92 93
 		consume_wdomain = Signal(depth_bits+1)
93  
-		self.specials += MultiReg(consume.q, consume_wdomain, "write")
  94
+		self.specials += [
  95
+			NoRetiming(consume.q),
  96
+			MultiReg(consume.q, consume_wdomain, "write")
  97
+		]
94 98
 		self.comb += [
95 99
 			self.writable.eq((produce.q[-1] == consume_wdomain[-1])
96 100
 			 | (produce.q[-2] == consume_wdomain[-2])

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