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  • 3 files changed
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  • 1 contributor
Showing with 45 additions and 14 deletions.
  1. +19 −1 migen/fhdl/verilog.py
  2. +17 −8 migen/genlib/cdc.py
  3. +9 −5 migen/genlib/fifo.py
20 migen/fhdl/verilog.py
View
@@ -230,7 +230,7 @@ def _call_special_classmethod(overrides, obj, method, *args, **kwargs):
else:
return None
-def _lower_specials(overrides, specials):
+def _lower_specials_step(overrides, specials):
f = Fragment()
lowered_specials = set()
for special in sorted(specials, key=lambda x: x.huid):
@@ -240,6 +240,24 @@ def _lower_specials(overrides, specials):
lowered_specials.add(special)
return f, lowered_specials
+def _can_lower(overrides, specials):
+ for special in specials:
+ cl = special.__class__
+ if cl in overrides:
+ cl = overrides[cl]
+ if hasattr(cl, "lower"):
+ return True
+ return False
+
+def _lower_specials(overrides, specials):
+ f, lowered_specials = _lower_specials_step(overrides, specials)
+ while _can_lower(overrides, f.specials):
+ f2, lowered_specials2 = _lower_specials_step(overrides, f.specials)
+ f += f2
+ lowered_specials |= lowered_specials2
+ f.specials -= lowered_specials2
+ return f, lowered_specials
+
def _printspecials(overrides, specials, ns):
r = ""
for special in sorted(specials, key=lambda x: x.huid):
25 migen/genlib/cdc.py
View
@@ -3,7 +3,17 @@
from migen.fhdl.specials import Special
from migen.fhdl.tools import list_signals
-class MultiRegImpl:
+class NoRetiming(Special):
+ def __init__(self, reg):
+ Special.__init__(self)
+ self.reg = reg
+
+ # do nothing
+ @staticmethod
+ def lower(dr):
+ return Module()
+
+class MultiRegImpl(Module):
def __init__(self, i, o, odomain, n):
self.i = i
self.o = o
@@ -12,16 +22,15 @@ def __init__(self, i, o, odomain, n):
w, signed = value_bits_sign(self.i)
self.regs = [Signal((w, signed)) for i in range(n)]
- def get_fragment(self):
+ ###
+
src = self.i
- o_sync = []
for reg in self.regs:
- o_sync.append(reg.eq(src))
+ sd = getattr(self.sync, self.odomain)
+ sd += reg.eq(src)
src = reg
- comb = [
- self.o.eq(src)
- ]
- return Fragment(comb, {self.odomain: o_sync})
+ self.comb += self.o.eq(src)
+ self.specials += [NoRetiming(reg) for reg in self.regs]
class MultiReg(Special):
def __init__(self, i, o, odomain="sys", n=2):
14 migen/genlib/fifo.py
View
@@ -1,7 +1,7 @@
from migen.fhdl.structure import *
from migen.fhdl.specials import Memory
from migen.fhdl.module import Module
-from migen.genlib.cdc import MultiReg, GrayCounter
+from migen.genlib.cdc import NoRetiming, MultiReg, GrayCounter
def _inc(signal, modulo):
if modulo == 2**len(signal):
@@ -85,12 +85,16 @@ def __init__(self, width, depth):
consume.ce.eq(self.readable & self.re)
]
- # TODO: disable retiming on produce.q and consume.q
-
produce_rdomain = Signal(depth_bits+1)
- self.specials += MultiReg(produce.q, produce_rdomain, "read")
+ self.specials += [
+ NoRetiming(produce.q),
+ MultiReg(produce.q, produce_rdomain, "read")
+ ]
consume_wdomain = Signal(depth_bits+1)
- self.specials += MultiReg(consume.q, consume_wdomain, "write")
+ self.specials += [
+ NoRetiming(consume.q),
+ MultiReg(consume.q, consume_wdomain, "write")
+ ]
self.comb += [
self.writable.eq((produce.q[-1] == consume_wdomain[-1])
| (produce.q[-2] == consume_wdomain[-2])

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