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12  examples/pytholite/basic.py
... ...
@@ -1,7 +1,7 @@
1 1
 from migen.flow.network import *
2 2
 from migen.flow.transactions import *
3 3
 from migen.actorlib.sim import *
4  
-from migen.pytholite.compiler import make_pytholite
  4
+from migen.pytholite.compiler import Pytholite
5 5
 from migen.sim.generic import Simulator
6 6
 from migen.fhdl import verilog
7 7
 
@@ -26,17 +26,23 @@ def run_sim(ng):
26 26
 	sim.run(30)
27 27
 	del sim
28 28
 
  29
+def make_ng_pytholite():
  30
+	ng_pytholite = Pytholite(number_gen)
  31
+	ng_pytholite.result = Source(layout)
  32
+	ng_pytholite.finalize()
  33
+	return ng_pytholite
  34
+
29 35
 def main():
30 36
 	print("Simulating native Python:")
31 37
 	ng_native = SimNumberGen()
32 38
 	run_sim(ng_native)
33 39
 	
34 40
 	print("Simulating Pytholite:")
35  
-	ng_pytholite = make_pytholite(number_gen, dataflow=[("result", Source, layout)])
  41
+	ng_pytholite = make_ng_pytholite()
36 42
 	run_sim(ng_pytholite)
37 43
 	
38 44
 	print("Converting Pytholite to Verilog:")
39  
-	ng_pytholite = make_pytholite(number_gen, dataflow=[("result", Source, layout)])
  45
+	ng_pytholite = make_ng_pytholite()
40 46
 	print(verilog.convert(ng_pytholite))
41 47
 
42 48
 main()
34  examples/pytholite/uio.py
@@ -5,7 +5,7 @@
5 5
 from migen.bus.transactions import *
6 6
 from migen.genlib.ioo import UnifiedIOSimulation
7 7
 from migen.pytholite.transel import Register
8  
-from migen.pytholite.compiler import make_pytholite
  8
+from migen.pytholite.compiler import Pytholite
9 9
 from migen.sim.generic import Simulator
10 10
 from migen.fhdl.module import Module
11 11
 from migen.fhdl.specials import Memory
@@ -37,7 +37,7 @@ def __init__(self, ng):
37 37
 		g.add_connection(ng, d)
38 38
 		
39 39
 		self.submodules.slave = wishbone.Target(SlaveModel())
40  
-		self.submodules.intercon = wishbone.InterconnectPointToPoint(ng.buses["wb"], self.slave.bus)
  40
+		self.submodules.intercon = wishbone.InterconnectPointToPoint(ng.wb, self.slave.bus)
41 41
 		self.submodules.ca = CompositeActor(g)
42 42
 
43 43
 def run_sim(ng):
@@ -45,30 +45,26 @@ def run_sim(ng):
45 45
 	sim.run(50)
46 46
 	del sim
47 47
 
  48
+def add_interfaces(obj):
  49
+	obj.result = Source(layout)
  50
+	obj.wb = wishbone.Interface()
  51
+	obj.mem = Memory(32, 3, init=[42, 37, 81])
  52
+	obj.finalize()
  53
+
48 54
 def main():
49  
-	mem = Memory(32, 3, init=[42, 37, 81])
50  
-	dataflow = [("result", Source, layout)]
51  
-	buses = {
52  
-		"wb":	wishbone.Interface(),
53  
-		"mem":	mem
54  
-	}
55  
-	
56 55
 	print("Simulating native Python:")
57  
-	ng_native = UnifiedIOSimulation(gen(), 
58  
-		dataflow=dataflow,
59  
-		buses=buses)
  56
+	ng_native = UnifiedIOSimulation(gen())
  57
+	add_interfaces(ng_native) 
60 58
 	run_sim(ng_native)
61 59
 	
62 60
 	print("Simulating Pytholite:")
63  
-	ng_pytholite = make_pytholite(gen,
64  
-		dataflow=dataflow,
65  
-		buses=buses)
  61
+	ng_pytholite = Pytholite(gen)
  62
+	add_interfaces(ng_pytholite)
66 63
 	run_sim(ng_pytholite)
67 64
 	
68 65
 	print("Converting Pytholite to Verilog:")
69  
-	ng_pytholite = make_pytholite(gen,
70  
-		dataflow=dataflow,
71  
-		buses=buses)
72  
-	print(verilog.convert(ng_pytholite.get_fragment()))
  66
+	ng_pytholite = Pytholite(gen)
  67
+	add_interfaces(ng_pytholite)
  68
+	print(verilog.convert(ng_pytholite))
73 69
 
74 70
 main()
8  migen/fhdl/visit.py
@@ -197,3 +197,11 @@ def visit_ArrayProxy(self, node):
197 197
 	
198 198
 	def visit_unknown(self, node):
199 199
 		return node
  200
+
  201
+class TransformModule:
  202
+	def __init__(self, transform, module):
  203
+		self.transform = transform
  204
+		self.module = module
  205
+
  206
+	def get_fragment(self):
  207
+		return self.transform(self.module.get_fragment())
29  migen/genlib/ioo.py
... ...
@@ -1,32 +1,37 @@
1 1
 from migen.fhdl.structure import *
2 2
 from migen.fhdl.specials import Memory
3 3
 from migen.flow.actor import *
  4
+from migen.flow.actor import _Endpoint
4 5
 from migen.flow.transactions import *
5 6
 from migen.actorlib.sim import TokenExchanger
6 7
 from migen.bus import wishbone, memory
7 8
 from migen.bus.transactions import *
8 9
 
9 10
 class UnifiedIOObject(Module):
10  
-	def __init__(self, dataflow=None, buses={}):
11  
-		if dataflow is not None:
  11
+	def do_finalize(self):
  12
+		if self.get_dataflow():
12 13
 			self.busy = Signal()
13  
-			for name, cl, layout in dataflow:
14  
-				setattr(self, name, cl(layout))
15  
-		self.buses = buses
16  
-		self.specials += set(v for v in self.buses.values() if isinstance(v, Memory))
  14
+		self.specials += set(v for v in self.__dict__.values() if isinstance(v, Memory))
  15
+
  16
+	def get_dataflow(self):
  17
+		return dict((k, v) for k, v in self.__dict__.items() if isinstance(v, _Endpoint))
  18
+
  19
+	def get_buses(self):
  20
+		return dict((k, v) for k, v in self.__dict__.items() if isinstance(v, (wishbone.Interface, Memory)))
17 21
 
18 22
 (_WAIT_COMPLETE, _WAIT_POLL) = range(2)
19 23
 
20 24
 class UnifiedIOSimulation(UnifiedIOObject):
21  
-	def __init__(self, generator, dataflow=None, buses={}):
  25
+	def __init__(self, generator):
22 26
 		self.generator = generator
23  
-		UnifiedIOObject.__init__(self, dataflow, buses)
24  
-		
  27
+
  28
+	def do_finalize(self):
  29
+		UnifiedIOObject.do_finalize(self)
25 30
 		callers = []
26 31
 		self.busname_to_caller_id = {}
27  
-		if dataflow is not None:
  32
+		if self.get_dataflow():
28 33
 			callers.append(TokenExchanger(self.dispatch_g(0), self))
29  
-		for k, v in self.buses.items():
  34
+		for k, v in self.get_buses().items():
30 35
 			caller_id = len(callers)
31 36
 			self.busname_to_caller_id[k] = caller_id
32 37
 			g = self.dispatch_g(caller_id)
@@ -34,8 +39,6 @@ def __init__(self, generator, dataflow=None, buses={}):
34 39
 				caller = wishbone.Initiator(g, v)
35 40
 			elif isinstance(v, Memory):
36 41
 				caller = memory.Initiator(g, v)
37  
-			else:
38  
-				raise NotImplementedError
39 42
 			callers.append(caller)
40 43
 		self.submodules += callers
41 44
 		
51  migen/pytholite/compiler.py
@@ -2,10 +2,13 @@
2 2
 import ast
3 3
 
4 4
 from migen.fhdl.structure import *
  5
+from migen.fhdl.visit import TransformModule
  6
+from migen.fhdl.specials import Memory
  7
+from migen.genlib.ioo import UnifiedIOObject
5 8
 from migen.pytholite.reg import *
6 9
 from migen.pytholite.expr import *
7 10
 from migen.pytholite import transel
8  
-from migen.pytholite.io import Pytholite, gen_io
  11
+from migen.pytholite.io import gen_io
9 12
 from migen.pytholite.fsm import *
10 13
 
11 14
 def _is_name_used(node, name):
@@ -226,23 +229,29 @@ def visit_expr_statement(self, sa, node):
226 229
 		else:
227 230
 			raise NotImplementedError
228 231
 
229  
-def make_pytholite(func, **ioresources):
230  
-	ioo = Pytholite(**ioresources)
231  
-	
232  
-	tree = ast.parse(inspect.getsource(func))
233  
-	symdict = func.__globals__.copy()
234  
-	registers = []
235  
-	
236  
-	states = _Compiler(ioo, symdict, registers).visit_top(tree)
237  
-	
238  
-	regf = Fragment()
239  
-	for register in registers:
240  
-		if register.source_encoding:
241  
-			register.finalize()
242  
-			regf += register.get_fragment()
243  
-	
244  
-	fsm = implement_fsm(states)
245  
-	fsmf = LowerAbstractLoad().visit(fsm.get_fragment())
246  
-	
247  
-	ioo.fragment = regf + fsmf
248  
-	return ioo
  232
+class Pytholite(UnifiedIOObject):
  233
+	def __init__(self, func):
  234
+		self.func = func
  235
+
  236
+	def do_finalize(self):
  237
+		UnifiedIOObject.do_finalize(self)
  238
+		if self.get_dataflow():
  239
+			self.busy.reset = 1
  240
+		self.memory_ports = dict((mem, mem.get_port(write_capable=True, we_granularity=8))
  241
+			for mem in self.__dict__.values() if isinstance(mem, Memory))
  242
+		self._compile()
  243
+
  244
+	def _compile(self):
  245
+		tree = ast.parse(inspect.getsource(self.func))
  246
+		symdict = self.func.__globals__.copy()
  247
+		registers = []
  248
+		
  249
+		states = _Compiler(self, symdict, registers).visit_top(tree)
  250
+		
  251
+		for register in registers:
  252
+			if register.source_encoding:
  253
+				register.finalize()
  254
+				self.submodules += register
  255
+		
  256
+		fsm = implement_fsm(states)
  257
+		self.submodules += TransformModule(LowerAbstractLoad().visit, fsm)
19  migen/pytholite/io.py
@@ -3,7 +3,6 @@
3 3
 
4 4
 from migen.fhdl.structure import *
5 5
 from migen.fhdl.specials import Memory
6  
-from migen.genlib.ioo import UnifiedIOObject
7 6
 from migen.flow.actor import Source, Sink
8 7
 from migen.flow.transactions import *
9 8
 from migen.bus import wishbone
@@ -11,17 +10,6 @@
11 10
 from migen.pytholite.fsm import *
12 11
 from migen.pytholite.expr import ExprCompiler
13 12
 
14  
-class Pytholite(UnifiedIOObject):
15  
-	def __init__(self, dataflow=None, buses={}):
16  
-		UnifiedIOObject.__init__(self, dataflow, buses)
17  
-		if dataflow is not None:
18  
-			self.busy.reset = 1
19  
-		self.memory_ports = dict((mem, mem.get_port(write_capable=True, we_granularity=8))
20  
-			for mem in self.buses.values() if isinstance(mem, Memory))
21  
-	
22  
-	def get_fragment(self):
23  
-		return UnifiedIOObject.get_fragment(self) + self.fragment
24  
-
25 13
 class _TokenPullExprCompiler(ExprCompiler):
26 14
 	def __init__(self, symdict, modelname, ep):
27 15
 		ExprCompiler.__init__(self, symdict)
@@ -151,11 +139,12 @@ def _gen_memory_io(compiler, modelname, model, to_model, from_model, port):
151 139
 def _gen_bus_io(compiler, modelname, model, to_model, from_model):
152 140
 	busname = ast.literal_eval(to_model["busname"])
153 141
 	if busname is None:
154  
-		if len(compiler.ioo.buses) != 1:
  142
+		buses = compiler.ioo.get_buses()
  143
+		if len(buses) != 1:
155 144
 			raise TypeError("Bus name not specified")
156  
-		bus = list(compiler.ioo.buses.values())[0]
  145
+		bus = list(buses.values())[0]
157 146
 	else:
158  
-		bus = compiler.ioo.buses[busname]
  147
+		bus = getattr(compiler.ioo, busname)
159 148
 	if isinstance(bus, wishbone.Interface):
160 149
 		return _gen_wishbone_io(compiler, modelname, model, to_model, from_model, bus)
161 150
 	elif isinstance(bus, Memory):
16  migen/pytholite/reg.py
... ...
@@ -1,6 +1,7 @@
1 1
 from operator import itemgetter
2 2
 
3 3
 from migen.fhdl.structure import *
  4
+from migen.fhdl.module import Module
4 5
 from migen.fhdl import visit as fhdl
5 6
 
6 7
 class AbstractLoad:
@@ -20,13 +21,12 @@ def visit_unknown(self, node):
20 21
 		else:
21 22
 			return node
22 23
 
23  
-class ImplRegister:
  24
+class ImplRegister(Module):
24 25
 	def __init__(self, name, bits_sign):
25 26
 		self.name = name
26 27
 		self.storage = Signal(bits_sign, name=self.name)
27 28
 		self.source_encoding = {}
28 29
 		self.id_to_source = {}
29  
-		self.finalized = False
30 30
 	
31 31
 	def load(self, source):
32 32
 		if id(source) not in self.source_encoding:
@@ -34,17 +34,9 @@ def load(self, source):
34 34
 			self.id_to_source[id(source)] = source
35 35
 		return AbstractLoad(self, source)
36 36
 	
37  
-	def finalize(self):
38  
-		if self.finalized:
39  
-			raise FinalizeError
  37
+	def do_finalize(self):
40 38
 		self.sel = Signal(max=len(self.source_encoding)+1, name="pl_regsel_"+self.name)
41  
-		self.finalized = True
42  
-	
43  
-	def get_fragment(self):
44  
-		if not self.finalized:
45  
-			raise FinalizeError
46 39
 		# do nothing when sel == 0
47 40
 		items = sorted(self.source_encoding.items(), key=itemgetter(1))
48 41
 		cases = dict((v, self.storage.eq(self.id_to_source[k])) for k, v in items)
49  
-		sync = [Case(self.sel, cases)]
50  
-		return Fragment(sync=sync)
  42
+		self.sync += Case(self.sel, cases)

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