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6  migen/bus/csr.py
@@ -61,14 +61,14 @@ def __init__(self, mem_or_size, address, read_only=None, bus=None):
61 61
 		else:
62 62
 			mem = Memory(data_width, mem_or_size//(data_width//8))
63 63
 		if mem.width > data_width:
64  
-			csrw_per_memw = (self.mem.width + data_width - 1)//data_width
  64
+			csrw_per_memw = (mem.width + data_width - 1)//data_width
65 65
 			word_bits = bits_for(csrw_per_memw-1)
66 66
 		else:
67 67
 			csrw_per_memw = 1
68 68
 			word_bits = 0
69 69
 		page_bits = _compute_page_bits(mem.depth + word_bits)
70 70
 		if page_bits:
71  
-			self._page = CSRStorage(page_bits, name=self.mem.name_override + "_page")
  71
+			self._page = CSRStorage(page_bits, name=mem.name_override + "_page")
72 72
 		else:
73 73
 			self._page = None
74 74
 		if read_only is None:
@@ -94,7 +94,7 @@ def __init__(self, mem_or_size, address, read_only=None, bus=None):
94 94
 		if word_bits:
95 95
 			word_index = Signal(word_bits)
96 96
 			word_expanded = Signal(csrw_per_memw*data_width)
97  
-			sync.append(word_index.eq(self.bus.adr[:word_bits]))
  97
+			self.sync += word_index.eq(self.bus.adr[:word_bits])
98 98
 			self.comb += [
99 99
 				word_expanded.eq(port.dat_r),
100 100
 				If(sel_r,
84  migen/fhdl/structure.py
@@ -109,6 +109,9 @@ def __getitem__(self, key):
109 109
 	
110 110
 	def eq(self, r):
111 111
 		return _Assign(self, r)
  112
+
  113
+	def __len__(self):
  114
+		return value_bits_sign(self)[0]
112 115
 	
113 116
 	def __hash__(self):
114 117
 		return HUID.__hash__(self)
@@ -164,9 +167,6 @@ def __init__(self, bits_sign=None, name=None, variable=False, reset=0, name_over
164 167
 		self.name_override = name_override
165 168
 		self.backtrace = tracer.trace_back(name)
166 169
 
167  
-	def __len__(self): # TODO: remove (use tools.value_bits_sign instead)
168  
-		return self.nbits
169  
-
170 170
 	def __repr__(self):
171 171
 		return "<Signal " + (self.backtrace[-1][0] or "anonymous") + " at " + hex(id(self)) + ">"
172 172
 
@@ -299,3 +299,81 @@ def __add__(self, other):
299 299
 			self.specials | other.specials,
300 300
 			self.clock_domains + other.clock_domains,
301 301
 			self.sim + other.sim)
  302
+
  303
+def value_bits_sign(v):
  304
+	if isinstance(v, bool):
  305
+		return 1, False
  306
+	elif isinstance(v, int):
  307
+		return bits_for(v), v < 0
  308
+	elif isinstance(v, Signal):
  309
+		return v.nbits, v.signed
  310
+	elif isinstance(v, (ClockSignal, ResetSignal)):
  311
+		return 1, False
  312
+	elif isinstance(v, _Operator):
  313
+		obs = list(map(value_bits_sign, v.operands))
  314
+		if v.op == "+" or v.op == "-":
  315
+			if not obs[0][1] and not obs[1][1]:
  316
+				# both operands unsigned
  317
+				return max(obs[0][0], obs[1][0]) + 1, False
  318
+			elif obs[0][1] and obs[1][1]:
  319
+				# both operands signed
  320
+				return max(obs[0][0], obs[1][0]) + 1, True
  321
+			elif not obs[0][1] and obs[1][1]:
  322
+				# first operand unsigned (add sign bit), second operand signed
  323
+				return max(obs[0][0] + 1, obs[1][0]) + 1, True
  324
+			else:
  325
+				# first signed, second operand unsigned (add sign bit)
  326
+				return max(obs[0][0], obs[1][0] + 1) + 1, True
  327
+		elif v.op == "*":
  328
+			if not obs[0][1] and not obs[1][1]:
  329
+				# both operands unsigned
  330
+				return obs[0][0] + obs[1][0]
  331
+			elif obs[0][1] and obs[1][1]:
  332
+				# both operands signed
  333
+				return obs[0][0] + obs[1][0] - 1
  334
+			else:
  335
+				# one operand signed, the other unsigned (add sign bit)
  336
+				return obs[0][0] + obs[1][0] + 1 - 1
  337
+		elif v.op == "<<<":
  338
+			if obs[1][1]:
  339
+				extra = 2**(obs[1][0] - 1) - 1
  340
+			else:
  341
+				extra = 2**obs[1][0] - 1
  342
+			return obs[0][0] + extra, obs[0][1]
  343
+		elif v.op == ">>>":
  344
+			if obs[1][1]:
  345
+				extra = 2**(obs[1][0] - 1)
  346
+			else:
  347
+				extra = 0
  348
+			return obs[0][0] + extra, obs[0][1]
  349
+		elif v.op == "&" or v.op == "^" or v.op == "|":
  350
+			if not obs[0][1] and not obs[1][1]:
  351
+				# both operands unsigned
  352
+				return max(obs[0][0], obs[1][0]), False
  353
+			elif obs[0][1] and obs[1][1]:
  354
+				# both operands signed
  355
+				return max(obs[0][0], obs[1][0]), True
  356
+			elif not obs[0][1] and obs[1][1]:
  357
+				# first operand unsigned (add sign bit), second operand signed
  358
+				return max(obs[0][0] + 1, obs[1][0]), True
  359
+			else:
  360
+				# first signed, second operand unsigned (add sign bit)
  361
+				return max(obs[0][0], obs[1][0] + 1), True
  362
+		elif v.op == "<" or v.op == "<=" or v.op == "==" or v.op == "!=" \
  363
+		  or v.op == ">" or v.op == ">=":
  364
+			  return 1, False
  365
+		elif v.op == "~":
  366
+			return obs[0]
  367
+		else:
  368
+			raise TypeError
  369
+	elif isinstance(v, _Slice):
  370
+		return v.stop - v.start, value_bits_sign(v.value)[1]
  371
+	elif isinstance(v, Cat):
  372
+		return sum(value_bits_sign(sv)[0] for sv in v.l), False
  373
+	elif isinstance(v, Replicate):
  374
+		return (value_bits_sign(v.v)[0])*v.n, False
  375
+	elif isinstance(v, _ArrayProxy):
  376
+		bsc = map(value_bits_sign, v.choices)
  377
+		return max(bs[0] for bs in bsc), any(bs[1] for bs in bsc)
  378
+	else:
  379
+		raise TypeError
80  migen/fhdl/tools.py
... ...
@@ -1,7 +1,7 @@
1 1
 import collections
2 2
 
3 3
 from migen.fhdl.structure import *
4  
-from migen.fhdl.structure import _Operator, _Slice, _Assign, _ArrayProxy
  4
+from migen.fhdl.structure import _Slice, _Assign
5 5
 from migen.fhdl.visit import NodeVisitor, NodeTransformer
6 6
 
7 7
 def bitreverse(s):
@@ -117,84 +117,6 @@ def insert_reset(rst, sl):
117 117
 	resetcode = [t.eq(t.reset) for t in sorted(targets, key=lambda x: x.huid)]
118 118
 	return [If(rst, *resetcode).Else(*sl)]
119 119
 
120  
-def value_bits_sign(v):
121  
-	if isinstance(v, bool):
122  
-		return 1, False
123  
-	elif isinstance(v, int):
124  
-		return bits_for(v), v < 0
125  
-	elif isinstance(v, Signal):
126  
-		return v.nbits, v.signed
127  
-	elif isinstance(v, (ClockSignal, ResetSignal)):
128  
-		return 1, False
129  
-	elif isinstance(v, _Operator):
130  
-		obs = list(map(value_bits_sign, v.operands))
131  
-		if v.op == "+" or v.op == "-":
132  
-			if not obs[0][1] and not obs[1][1]:
133  
-				# both operands unsigned
134  
-				return max(obs[0][0], obs[1][0]) + 1, False
135  
-			elif obs[0][1] and obs[1][1]:
136  
-				# both operands signed
137  
-				return max(obs[0][0], obs[1][0]) + 1, True
138  
-			elif not obs[0][1] and obs[1][1]:
139  
-				# first operand unsigned (add sign bit), second operand signed
140  
-				return max(obs[0][0] + 1, obs[1][0]) + 1, True
141  
-			else:
142  
-				# first signed, second operand unsigned (add sign bit)
143  
-				return max(obs[0][0], obs[1][0] + 1) + 1, True
144  
-		elif v.op == "*":
145  
-			if not obs[0][1] and not obs[1][1]:
146  
-				# both operands unsigned
147  
-				return obs[0][0] + obs[1][0]
148  
-			elif obs[0][1] and obs[1][1]:
149  
-				# both operands signed
150  
-				return obs[0][0] + obs[1][0] - 1
151  
-			else:
152  
-				# one operand signed, the other unsigned (add sign bit)
153  
-				return obs[0][0] + obs[1][0] + 1 - 1
154  
-		elif v.op == "<<<":
155  
-			if obs[1][1]:
156  
-				extra = 2**(obs[1][0] - 1) - 1
157  
-			else:
158  
-				extra = 2**obs[1][0] - 1
159  
-			return obs[0][0] + extra, obs[0][1]
160  
-		elif v.op == ">>>":
161  
-			if obs[1][1]:
162  
-				extra = 2**(obs[1][0] - 1)
163  
-			else:
164  
-				extra = 0
165  
-			return obs[0][0] + extra, obs[0][1]
166  
-		elif v.op == "&" or v.op == "^" or v.op == "|":
167  
-			if not obs[0][1] and not obs[1][1]:
168  
-				# both operands unsigned
169  
-				return max(obs[0][0], obs[1][0]), False
170  
-			elif obs[0][1] and obs[1][1]:
171  
-				# both operands signed
172  
-				return max(obs[0][0], obs[1][0]), True
173  
-			elif not obs[0][1] and obs[1][1]:
174  
-				# first operand unsigned (add sign bit), second operand signed
175  
-				return max(obs[0][0] + 1, obs[1][0]), True
176  
-			else:
177  
-				# first signed, second operand unsigned (add sign bit)
178  
-				return max(obs[0][0], obs[1][0] + 1), True
179  
-		elif v.op == "<" or v.op == "<=" or v.op == "==" or v.op == "!=" \
180  
-		  or v.op == ">" or v.op == ">=":
181  
-			  return 1, False
182  
-		elif v.op == "~":
183  
-			return obs[0]
184  
-		else:
185  
-			raise TypeError
186  
-	elif isinstance(v, _Slice):
187  
-		return v.stop - v.start, value_bits_sign(v.value)[1]
188  
-	elif isinstance(v, Cat):
189  
-		return sum(value_bits_sign(sv)[0] for sv in v.l), False
190  
-	elif isinstance(v, Replicate):
191  
-		return (value_bits_sign(v.v)[0])*v.n, False
192  
-	elif isinstance(v, _ArrayProxy):
193  
-		bsc = map(value_bits_sign, v.choices)
194  
-		return max(bs[0] for bs in bsc), any(bs[1] for bs in bsc)
195  
-	else:
196  
-		raise TypeError
197  
-
198 120
 # Basics are FHDL structure elements that back-ends are not required to support
199 121
 # but can be expressed in terms of other elements (lowered) before conversion.
200 122
 class _BasicLowerer(NodeTransformer):
2  migen/genlib/cdc.py
... ...
@@ -1,6 +1,6 @@
1 1
 from migen.fhdl.structure import *
2 2
 from migen.fhdl.specials import Special
3  
-from migen.fhdl.tools import value_bits_sign, list_signals
  3
+from migen.fhdl.tools import list_signals
4 4
 
5 5
 class MultiRegImpl:
6 6
 	def __init__(self, i, o, odomain, n):

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