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  • 2 commits
  • 2 files changed
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Showing with 29 additions and 18 deletions.
  1. +5 −17 examples/basic/memory.py
  2. +24 −1 migen/fhdl/structure.py
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22 examples/basic/memory.py
@@ -1,23 +1,11 @@
from migen.fhdl.structure import *
from migen.fhdl import verilog
-d = 100
-d_b = bits_for(d-1)
-w = 32
+mem = Memory(32, 100, init=[5, 18, 32])
+p1 = mem.get_port(write_capable=True, we_granularity=8)
+p2 = mem.get_port(has_re=True, clock_domain="rd")
-a1 = Signal(BV(d_b))
-d1 = Signal(BV(w))
-we1 = Signal(BV(4))
-dw1 = Signal(BV(w))
-re = Signal()
-p1 = MemoryPort(a1, d1, we1, dw1, we_granularity=8)
-
-a2 = Signal(BV(d_b))
-d2 = Signal(BV(w))
-re2 = Signal()
-p2 = MemoryPort(a2, d2, re=re2, clock_domain="rd")
-
-mem = Memory(w, d, p1, p2, init=[5, 18, 32])
f = Fragment(memories=[mem])
-v = verilog.convert(f, ios={a1, d1, we1, dw1, a2, d2, re2})
+v = verilog.convert(f, ios={p1.adr, p1.dat_r, p1.we, p1.dat_w,
+ p2.adr, p2.dat_r, p2.re})
print(v)
View
25 migen/fhdl/structure.py
@@ -308,6 +308,7 @@ def get_io(self, name):
(READ_FIRST, WRITE_FIRST, NO_CHANGE) = range(3)
+# NOTE: Direct use of MemoryPort is deprecated. Use Memory.get_port() instead.
class MemoryPort:
def __init__(self, adr, dat_r, we=None, dat_w=None,
async_read=False, re=None, we_granularity=0, mode=WRITE_FIRST,
@@ -322,13 +323,35 @@ def __init__(self, adr, dat_r, we=None, dat_w=None,
self.mode = mode
self.clock_domain = clock_domain
+# NOTE: ports parameter will be removed
class Memory(HUID):
def __init__(self, width, depth, *ports, init=None):
super().__init__()
self.width = width
self.depth = depth
- self.ports = ports
+ self.ports = list(ports)
self.init = init
+
+ def get_port(self, write_capable=False, async_read=False,
+ has_re=False, we_granularity=0, mode=WRITE_FIRST,
+ clock_domain="sys"):
+ adr = Signal(BV(bits_for(self.depth-1)))
+ dat_r = Signal(BV(self.width))
+ if write_capable:
+ we = Signal()
+ dat_w = Signal(BV(self.width))
+ else:
+ we = None
+ dat_w = None
+ if has_re:
+ re = Signal()
+ else:
+ re = None
+ mp = MemoryPort(adr, dat_r, we, dat_w,
+ async_read, re, we_granularity, mode,
+ clock_domain)
+ self.ports.append(mp)
+ return mp
#

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