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  • 4 commits
  • 3 files changed
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  • 1 contributor
16  migen/bank/csrgen.py
@@ -113,20 +113,20 @@ def scan(self):
113 113
 					mapaddr = self.address_map(name, memory)
114 114
 					mmap = csr.SRAM(memory, mapaddr)
115 115
 					registers += mmap.get_registers()
116  
-					self.srams.append(mmap)
  116
+					self.srams.append((name, memory, mmap))
117 117
 			if registers:
118 118
 				mapaddr = self.address_map(name, None)
119 119
 				rmap = Bank(registers, mapaddr)
120  
-				self.banks.append(rmap)
  120
+				self.banks.append((name, rmap))
121 121
 
122  
-	def get_banks(self):
123  
-		return self.banks
  122
+	def get_rmaps(self):
  123
+		return [rmap for name, rmap in self.banks]
124 124
 
125  
-	def get_srams(self):
126  
-		return self.srams
  125
+	def get_mmaps(self):
  126
+		return [mmap for name, memory, mmap in self.srams]
127 127
 
128 128
 	def get_buses(self):
129  
-		return [i.bus for i in self.banks + self.srams]
  129
+		return [i.bus for i in self.get_rmaps() + self.get_mmaps()]
130 130
 
131 131
 	def get_fragment(self):
132  
-		return sum([i.get_fragment() for i in self.banks + self.srams], Fragment())
  132
+		return sum([i.get_fragment() for i in self.get_rmaps() + self.get_mmaps()], Fragment())
6  migen/bank/description.py
@@ -19,6 +19,9 @@ def __init__(self, size=1, name=None):
19 19
 		self.r = Signal(self.size)
20 20
 		self.w = Signal(self.size)
21 21
 
  22
+	def get_size(self):
  23
+		return self.size
  24
+
22 25
 (READ_ONLY, WRITE_ONLY, READ_WRITE) = range(3)
23 26
 
24 27
 class Field:
@@ -45,6 +48,9 @@ def __init__(self, *fields, name=None):
45 48
 		_Register.__init__(self, name)
46 49
 		self.fields = fields
47 50
 
  51
+	def get_size(self):
  52
+		return sum(field.size for field in self.fields)
  53
+
48 54
 class RegisterField(RegisterFields):
49 55
 	def __init__(self, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, reset=0, atomic_write=False, name=None):
50 56
 		self.field = Field(size, access_bus, access_dev, reset, atomic_write, name="")
8  migen/genlib/record.py
@@ -27,10 +27,14 @@ def __init__(self, layout, name=""):
27 27
 				setattr(self, f, Signal(1, prefix + f))
28 28
 				self.field_order.append((f, 1))
29 29
 
  30
+	def eq(self, other):
  31
+		return [getattr(self, key).eq(getattr(other, key))
  32
+		  for key, a in self.field_order]
  33
+
30 34
 	def layout(self):
31 35
 		l = []
32 36
 		for key, alignment in self.field_order:
33  
-			e = self.__dict__[key]
  37
+			e = getattr(self, key)
34 38
 			if isinstance(e, Signal):
35 39
 				l.append((key, (e.nbits, e.signed), alignment))
36 40
 			elif isinstance(e, Record):
@@ -80,7 +84,7 @@ def flatten(self, align=False, offset=0, return_offset=False):
80 84
 					l.append(Replicate(0, pad_size))
81 85
 					offset += pad_size
82 86
 			
83  
-			e = self.__dict__[key]
  87
+			e = getattr(self, key)
84 88
 			if isinstance(e, Signal):
85 89
 				added = [e]
86 90
 			elif isinstance(e, Record):

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