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  • 4 commits
  • 3 files changed
  • 0 commit comments
  • 1 contributor
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16 migen/bank/csrgen.py
@@ -113,20 +113,20 @@ def scan(self):
mapaddr = self.address_map(name, memory)
mmap = csr.SRAM(memory, mapaddr)
registers += mmap.get_registers()
- self.srams.append(mmap)
+ self.srams.append((name, memory, mmap))
if registers:
mapaddr = self.address_map(name, None)
rmap = Bank(registers, mapaddr)
- self.banks.append(rmap)
+ self.banks.append((name, rmap))
- def get_banks(self):
- return self.banks
+ def get_rmaps(self):
+ return [rmap for name, rmap in self.banks]
- def get_srams(self):
- return self.srams
+ def get_mmaps(self):
+ return [mmap for name, memory, mmap in self.srams]
def get_buses(self):
- return [i.bus for i in self.banks + self.srams]
+ return [i.bus for i in self.get_rmaps() + self.get_mmaps()]
def get_fragment(self):
- return sum([i.get_fragment() for i in self.banks + self.srams], Fragment())
+ return sum([i.get_fragment() for i in self.get_rmaps() + self.get_mmaps()], Fragment())
View
6 migen/bank/description.py
@@ -19,6 +19,9 @@ def __init__(self, size=1, name=None):
self.r = Signal(self.size)
self.w = Signal(self.size)
+ def get_size(self):
+ return self.size
+
(READ_ONLY, WRITE_ONLY, READ_WRITE) = range(3)
class Field:
@@ -45,6 +48,9 @@ def __init__(self, *fields, name=None):
_Register.__init__(self, name)
self.fields = fields
+ def get_size(self):
+ return sum(field.size for field in self.fields)
+
class RegisterField(RegisterFields):
def __init__(self, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, reset=0, atomic_write=False, name=None):
self.field = Field(size, access_bus, access_dev, reset, atomic_write, name="")
View
8 migen/genlib/record.py
@@ -27,10 +27,14 @@ def __init__(self, layout, name=""):
setattr(self, f, Signal(1, prefix + f))
self.field_order.append((f, 1))
+ def eq(self, other):
+ return [getattr(self, key).eq(getattr(other, key))
+ for key, a in self.field_order]
+
def layout(self):
l = []
for key, alignment in self.field_order:
- e = self.__dict__[key]
+ e = getattr(self, key)
if isinstance(e, Signal):
l.append((key, (e.nbits, e.signed), alignment))
elif isinstance(e, Record):
@@ -80,7 +84,7 @@ def flatten(self, align=False, offset=0, return_offset=False):
l.append(Replicate(0, pad_size))
offset += pad_size
- e = self.__dict__[key]
+ e = getattr(self, key)
if isinstance(e, Signal):
added = [e]
elif isinstance(e, Record):

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