Skip to content

HTTPS clone URL

Subversion checkout URL

You can clone with HTTPS or Subversion.

Download ZIP

Comparing changes

Choose two branches to see what's changed or to start a new pull request. If you need to, you can also compare across forks.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also compare across forks.
  • 2 commits
  • 2 files changed
  • 0 commit comments
  • 1 contributor
Showing with 79 additions and 3 deletions.
  1. +15 −3 migen/fhdl/module.py
  2. +64 −0 migen/genlib/fifo.py
View
18 migen/fhdl/module.py
@@ -67,11 +67,11 @@ def __iadd__(self, other):
class _ModuleSubmodules(_ModuleProxy):
def __setattr__(self, name, value):
- self._fm._submodules += [(name, e) for e in _flat_list(value)]
+ self._fm._submodules += [(name, e, dict()) for e in _flat_list(value)]
setattr(self._fm, name, value)
def __iadd__(self, other):
- self._fm._submodules += [(None, e) for e in _flat_list(other)]
+ self._fm._submodules += [(None, e, dict()) for e in _flat_list(other)]
return self
class _ModuleClockDomains(_ModuleProxy, _ModuleForwardAttr):
@@ -130,8 +130,20 @@ def __setattr__(self, name, value):
else:
object.__setattr__(self, name, value)
+ def add_submodule(self, submodule, cd_remapping=dict(), name=None):
+ if isinstance(cd_remapping, str):
+ cd_remapping = {"sys": cd_remapping}
+ if name is not None:
+ setattr(self, name, submodule)
+ self._submodules.append((name, submodule, cd_remapping))
+
def _collect_submodules(self):
- r = [(name, submodule.get_fragment()) for name, submodule in self._submodules]
+ r = []
+ for name, submodule, cd_remapping in self._submodules:
+ f = submodule.get_fragment()
+ for old, new in cd_remapping.items():
+ rename_clock_domain(f, old, new)
+ r.append((name, f))
self._submodules = []
return r
View
64 migen/genlib/fifo.py
@@ -0,0 +1,64 @@
+from migen.fhdl.structure import *
+from migen.fhdl.specials import Memory
+from migen.fhdl.module import Module
+
+def _inc(signal, modulo):
+ if modulo == 2**len(signal):
+ return signal.eq(signal + 1)
+ else:
+ return If(signal == (modulo - 1),
+ signal.eq(0)
+ ).Else(
+ signal.eq(signal + 1)
+ )
+
+class SyncFIFO(Module):
+ def __init__(self, width, depth):
+ self.din = Signal(width)
+ self.we = Signal()
+ self.writable = Signal() # not full
+ self.dout = Signal(width)
+ self.re = Signal()
+ self.readable = Signal() # not empty
+
+ ###
+
+ do_write = Signal()
+ do_read = Signal()
+ self.comb += [
+ do_write.eq(self.writable & self.we),
+ do_read.eq(self.readable & self.re)
+ ]
+
+ level = Signal(max=depth+1)
+ produce = Signal(max=depth)
+ consume = Signal(max=depth)
+ storage = Memory(width, depth)
+ self.specials += storage
+
+ wrport = storage.get_port(write_capable=True)
+ self.comb += [
+ wrport.adr.eq(produce),
+ wrport.dat_w.eq(self.din),
+ wrport.we.eq(do_write)
+ ]
+ self.sync += If(do_write, _inc(produce, depth))
+
+ rdport = storage.get_port(async_read=True)
+ self.comb += [
+ rdport.adr.eq(consume),
+ self.dout.eq(rdport.dat_r)
+ ]
+ self.sync += If(do_read, _inc(consume, depth))
+
+ self.sync += [
+ If(do_write,
+ If(~do_read, level.eq(level + 1))
+ ).Elif(do_read,
+ level.eq(level - 1)
+ )
+ ]
+ self.comb += [
+ self.writable.eq(level != depth),
+ self.readable.eq(level != 0)
+ ]

No commit comments for this range

Something went wrong with that request. Please try again.