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  • 5 commits
  • 6 files changed
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  • 2 contributors
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16 examples/basic/reslice.py
@@ -0,0 +1,16 @@
+from migen.fhdl.std import *
+from migen.fhdl import verilog
+
+class Example(Module):
+ def __init__(self):
+ a = Signal(3)
+ b = Signal(4)
+ c = Signal(5)
+ d = Signal(7)
+ s1 = c[:3][:2]
+ s2 = Cat(a, b)[:6]
+ s3 = Cat(s1, s2)[-5:]
+ self.comb += s3.eq(0)
+ self.comb += d.eq(Cat(d[::-1], Cat(s1[:1], s3[-4:])[:3]))
+
+print(verilog.convert(Example()))
View
13 migen/fhdl/structure.py
@@ -75,16 +75,9 @@ def __getitem__(self, key):
key += flen(self)
return _Slice(self, key, key+1)
elif isinstance(key, slice):
- start = key.start or 0
- stop = key.stop or flen(self)
- if start < 0:
- start += flen(self)
- if stop < 0:
- stop += flen(self)
- if stop > flen(self):
- stop = flen(self)
- if key.step != None:
- raise KeyError
+ start, stop, step = key.indices(flen(self))
+ if step != 1:
+ return Cat(*(self[i] for i in range(start, stop, step)))
return _Slice(self, start, stop)
else:
raise KeyError
View
53 migen/fhdl/tools.py
@@ -119,14 +119,11 @@ def generate_reset(rst, sl):
def insert_reset(rst, sl):
return [If(rst, *generate_reset(rst, sl)).Else(*sl)]
-# Basics are FHDL structure elements that back-ends are not required to support
-# but can be expressed in terms of other elements (lowered) before conversion.
-class _BasicLowerer(NodeTransformer):
- def __init__(self, clock_domains):
- self.comb = []
+class _Lowerer(NodeTransformer):
+ def __init__(self):
self.target_context = False
self.extra_stmts = []
- self.clock_domains = clock_domains
+ self.comb = []
def visit_Assign(self, node):
old_target_context, old_extra_stmts = self.target_context, self.extra_stmts
@@ -142,7 +139,14 @@ def visit_Assign(self, node):
self.target_context, self.extra_stmts = old_target_context, old_extra_stmts
return r
-
+
+# Basics are FHDL structure elements that back-ends are not required to support
+# but can be expressed in terms of other elements (lowered) before conversion.
+class _BasicLowerer(_Lowerer):
+ def __init__(self, clock_domains):
+ self.clock_domains = clock_domains
+ _Lowerer.__init__(self)
+
def visit_ArrayProxy(self, node):
array_muxed = Signal(value_bits_sign(node), variable=True)
if self.target_context:
@@ -163,26 +167,43 @@ def visit_ClockSignal(self, node):
def visit_ResetSignal(self, node):
return self.clock_domains[node.cd].rst
-def lower_basics(f):
- bl = _BasicLowerer(f.clock_domains)
- f = bl.visit(f)
- f.comb += bl.comb
+class _ComplexSliceLowerer(_Lowerer):
+ def visit_Slice(self, node):
+ if not isinstance(node.value, Signal):
+ slice_proxy = Signal(value_bits_sign(node.value))
+ if self.target_context:
+ a = _Assign(node.value, slice_proxy)
+ else:
+ a = _Assign(slice_proxy, node.value)
+ self.comb.append(self.visit_Assign(a))
+ node = _Slice(slice_proxy, node.start, node.stop)
+ return NodeTransformer.visit_Slice(self, node)
+
+def _apply_lowerer(l, f):
+ f = l.visit(f)
+ f.comb += l.comb
for special in f.specials:
for obj, attr, direction in special.iter_expressions():
if direction != SPECIAL_INOUT:
# inouts are only supported by Migen when connected directly to top-level
# in this case, they are Signal and never need lowering
- bl.comb = []
- bl.target_context = direction != SPECIAL_INPUT
- bl.extra_stmts = []
+ l.comb = []
+ l.target_context = direction != SPECIAL_INPUT
+ l.extra_stmts = []
expr = getattr(obj, attr)
- expr = bl.visit(expr)
+ expr = l.visit(expr)
setattr(obj, attr, expr)
- f.comb += bl.comb + bl.extra_stmts
+ f.comb += l.comb + l.extra_stmts
return f
+def lower_basics(f):
+ return _apply_lowerer(_BasicLowerer(f.clock_domains), f)
+
+def lower_complex_slices(f):
+ return _apply_lowerer(_ComplexSliceLowerer(), f)
+
class _ClockDomainRenamer(NodeVisitor):
def __init__(self, old, new):
self.old = old
View
1  migen/fhdl/verilog.py
@@ -302,6 +302,7 @@ def convert(f, ios=None, name="top",
else:
raise KeyError("Unresolved clock domain: '"+cd_name+"'")
+ f = lower_complex_slices(f)
_insert_resets(f)
f = lower_basics(f)
fs, lowered_specials = _lower_specials(special_overrides, f.specials)
View
8 migen/genlib/coding.py
@@ -22,10 +22,8 @@ def __init__(self, width):
self.i = Signal(width) # one-hot, lsb has priority
self.o = Signal(max=width) # binary
self.n = Signal() # none
- act = If(0)
- for j in range(width):
- act = act.Elif(self.i[j], self.o.eq(j))
- self.comb += act
+ for j in range(width)[::-1]: # last has priority
+ self.comb += If(self.i[j], self.o.eq(j))
self.comb += self.n.eq(self.i == 0)
class Decoder(Module):
@@ -41,9 +39,7 @@ class PriorityDecoder(Decoder):
pass # same
def _main():
- from migen.sim.generic import Simulator, TopLevel
from migen.fhdl import verilog
-
e = Encoder(8)
print(verilog.convert(e, ios={e.i, e.o, e.n}))
pe = PriorityEncoder(8)
View
6 migen/genlib/misc.py
@@ -1,12 +1,6 @@
from migen.fhdl.std import *
-from migen.fhdl.tools import value_bits_sign
from migen.fhdl.structure import _Operator
-def bitreverse(s):
- length, signed = value_bits_sign(s)
- l = [s[i] for i in reversed(range(length))]
- return Cat(*l)
-
def optree(op, operands, lb=None, ub=None, default=None):
if lb is None:
lb = 0

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