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  • 2 commits
  • 1 file changed
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  • 2 contributors
Commits on Nov 02, 2013
@enjoy-digital enjoy-digital actorlib/spi: add ack_when_inactive parameter to DMA Write Controller
In some cases we don't want to stall the input pipeline when the DMA is inactive, setting ack_when_inactive to True will enable acknowledge of data when the DMA is inactive.
e0e99ec
@sbourdeauducq sbourdeauducq actorlib/spi/DMAWriteController: make ack_when_inactive a keyword-onl…
…y arg
c3aad93
Showing with 15 additions and 3 deletions.
  1. +15 −3 migen/actorlib/spi.py
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18 migen/actorlib/spi.py
@@ -157,21 +157,33 @@ def __init__(self, bus_accessor, *args, **kwargs):
self.comb += self.r_busy.status.eq(self.busy)
class DMAWriteController(_DMAController):
- def __init__(self, bus_accessor, *args, **kwargs):
+ def __init__(self, bus_accessor, *args, ack_when_inactive=False, **kwargs):
bus_aw = flen(bus_accessor.address_data.payload.a)
bus_dw = flen(bus_accessor.address_data.payload.d)
_DMAController.__init__(self, bus_accessor, bus_aw, bus_dw, *args, **kwargs)
g = DataFlowGraph()
adr_buffer = AbstractActor(plumbing.Buffer)
+ int_sequence = misc.IntSequence(bus_aw, bus_aw)
g.add_pipeline(self.generator,
- misc.IntSequence(bus_aw, bus_aw),
+ int_sequence,
adr_buffer)
g.add_connection(adr_buffer, bus_accessor, sink_subr=["a"])
g.add_connection(AbstractActor(plumbing.Buffer), bus_accessor, sink_subr=["d"])
comp_actor = CompositeActor(g)
self.submodules += comp_actor
- self.data = comp_actor.d
+ if ack_when_inactive:
+ demultiplexer = plumbing.Demultiplexer(comp_actor.d.payload.layout, 2)
+ self.comb +=[
+ demultiplexer.sel.eq(~adr_buffer.busy),
+ demultiplexer.source0.connect(comp_actor.d),
+ demultiplexer.source1.ack.eq(1),
+ ]
+ self.submodules += demultiplexer
+ self.data = demultiplexer.sink
+ else:
+ self.data = comp_actor.d
+
self.busy = comp_actor.busy
self.comb += self.r_busy.status.eq(self.busy)

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