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  • 2 commits
  • 3 files changed
  • 0 commit comments
  • 1 contributor
Showing with 17 additions and 16 deletions.
  1. +12 −11 migen/bus/csr.py
  2. +0 −5 migen/fhdl/tools.py
  3. +5 −0 migen/genlib/misc.py
View
23 migen/bus/csr.py
@@ -58,13 +58,9 @@ def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
mem = mem_or_size
else:
mem = Memory(data_width, mem_or_size//(data_width//8), init=init)
- if mem.width > data_width:
- csrw_per_memw = (mem.width + data_width - 1)//data_width
- word_bits = bits_for(csrw_per_memw-1)
- else:
- csrw_per_memw = 1
- word_bits = 0
- page_bits = _compute_page_bits(mem.depth + word_bits)
+ csrw_per_memw = (mem.width + data_width - 1)//data_width
+ word_bits = log2_int(csrw_per_memw)
+ page_bits = log2_int(mem.depth*csrw_per_memw, False)
if page_bits:
self._page = CSRStorage(page_bits, name=mem.name_override + "_page")
else:
@@ -80,8 +76,7 @@ def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
###
- port = mem.get_port(write_capable=not read_only,
- we_granularity=data_width if not read_only and word_bits else 0)
+ port = mem.get_port(write_capable=not read_only)
self.specials += mem, port
sel = Signal()
@@ -100,9 +95,15 @@ def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
)
]
if not read_only:
+ wregs = []
+ for i in range(csrw_per_memw-1):
+ wreg = Signal(data_width)
+ self.sync += If(sel & self.bus.we & (self.bus.adr[:word_bits] == i), wreg.eq(self.bus.dat_w))
+ wregs.append(wreg)
+ memword_chunks = [self.bus.dat_w] + list(reversed(wregs))
self.comb += [
- If(sel & self.bus.we, port.we.eq((1 << word_bits) >> self.bus.adr[:self.word_bits])),
- port.dat_w.eq(Replicate(self.bus.dat_w, csrw_per_memw))
+ port.we.eq(sel & self.bus.we & (self.bus.adr[:word_bits] == csrw_per_memw - 1)),
+ port.dat_w.eq(Cat(*memword_chunks))
]
else:
self.comb += If(sel_r, self.bus.dat_r.eq(port.dat_r))
View
5 migen/fhdl/tools.py
@@ -5,11 +5,6 @@
from migen.fhdl.visit import NodeVisitor, NodeTransformer
from migen.fhdl.size import value_bits_sign
-def bitreverse(s):
- length, signed = value_bits_sign(s)
- l = [s[i] for i in reversed(range(length))]
- return Cat(*l)
-
def flat_iteration(l):
for element in l:
if isinstance(element, collections.Iterable):
View
5 migen/genlib/misc.py
@@ -1,6 +1,11 @@
from migen.fhdl.std import *
from migen.fhdl.structure import _Operator
+def bitreverse(s):
+ length, signed = value_bits_sign(s)
+ l = [s[i] for i in reversed(range(length))]
+ return Cat(*l)
+
def optree(op, operands, lb=None, ub=None, default=None):
if lb is None:
lb = 0

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