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23  migen/bus/csr.py
@@ -58,13 +58,9 @@ def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
58 58
 			mem = mem_or_size
59 59
 		else:
60 60
 			mem = Memory(data_width, mem_or_size//(data_width//8), init=init)
61  
-		if mem.width > data_width:
62  
-			csrw_per_memw = (mem.width + data_width - 1)//data_width
63  
-			word_bits = bits_for(csrw_per_memw-1)
64  
-		else:
65  
-			csrw_per_memw = 1
66  
-			word_bits = 0
67  
-		page_bits = _compute_page_bits(mem.depth + word_bits)
  61
+		csrw_per_memw = (mem.width + data_width - 1)//data_width
  62
+		word_bits = log2_int(csrw_per_memw)
  63
+		page_bits = log2_int(mem.depth*csrw_per_memw, False)
68 64
 		if page_bits:
69 65
 			self._page = CSRStorage(page_bits, name=mem.name_override + "_page")
70 66
 		else:
@@ -80,8 +76,7 @@ def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
80 76
 	
81 77
 		###
82 78
 
83  
-		port = mem.get_port(write_capable=not read_only,
84  
-			we_granularity=data_width if not read_only and word_bits else 0)
  79
+		port = mem.get_port(write_capable=not read_only)
85 80
 		self.specials += mem, port
86 81
 		
87 82
 		sel = Signal()
@@ -100,9 +95,15 @@ def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
100 95
 				)
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 			]
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 			if not read_only:
  98
+				wregs = []
  99
+				for i in range(csrw_per_memw-1):
  100
+					wreg = Signal(data_width)
  101
+					self.sync += If(sel & self.bus.we & (self.bus.adr[:word_bits] == i), wreg.eq(self.bus.dat_w))
  102
+					wregs.append(wreg)
  103
+				memword_chunks = [self.bus.dat_w] + list(reversed(wregs))
103 104
 				self.comb += [
104  
-					If(sel & self.bus.we, port.we.eq((1 << word_bits) >> self.bus.adr[:self.word_bits])),
105  
-					port.dat_w.eq(Replicate(self.bus.dat_w, csrw_per_memw))
  105
+					port.we.eq(sel & self.bus.we & (self.bus.adr[:word_bits] == csrw_per_memw - 1)),
  106
+					port.dat_w.eq(Cat(*memword_chunks))
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 				]
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 		else:
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 			self.comb += If(sel_r, self.bus.dat_r.eq(port.dat_r))
5  migen/fhdl/tools.py
@@ -5,11 +5,6 @@
5 5
 from migen.fhdl.visit import NodeVisitor, NodeTransformer
6 6
 from migen.fhdl.size import value_bits_sign
7 7
 
8  
-def bitreverse(s):
9  
-	length, signed = value_bits_sign(s)
10  
-	l = [s[i] for i in reversed(range(length))]
11  
-	return Cat(*l)
12  
-
13 8
 def flat_iteration(l):
14 9
 	for element in l:
15 10
 		if isinstance(element, collections.Iterable):
5  migen/genlib/misc.py
... ...
@@ -1,6 +1,11 @@
1 1
 from migen.fhdl.std import *
2 2
 from migen.fhdl.structure import _Operator
3 3
 
  4
+def bitreverse(s):
  5
+	length, signed = value_bits_sign(s)
  6
+	l = [s[i] for i in reversed(range(length))]
  7
+	return Cat(*l)
  8
+
4 9
 def optree(op, operands, lb=None, ub=None, default=None):
5 10
 	if lb is None:
6 11
 		lb = 0

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