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Showing 1 changed file with 3 additions and 10 deletions. Show diff stats Hide diff stats

  1. 13  migen/bus/csr.py
13  migen/bus/csr.py
@@ -45,13 +45,6 @@ def do_simulation(self, s):
45 45
 					s.wr(self.bus.we, 1)
46 46
 					s.wr(self.bus.dat_w, self.transaction.data)
47 47
 
48  
-def _compute_page_bits(nwords):
49  
-	npages = (nwords - 1)//512
50  
-	if npages > 0:
51  
-		return bits_for(npages-1)
52  
-	else:
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-		return 0
54  
-
55 48
 class SRAM(Module):
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 	def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
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 		if isinstance(mem_or_size, Memory):
@@ -60,7 +53,7 @@ def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
60 53
 			mem = Memory(data_width, mem_or_size//(data_width//8), init=init)
61 54
 		csrw_per_memw = (mem.width + data_width - 1)//data_width
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 		word_bits = log2_int(csrw_per_memw)
63  
-		page_bits = log2_int(mem.depth*csrw_per_memw, False)
  56
+		page_bits = log2_int((mem.depth*csrw_per_memw + 511)//512, False)
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 		if page_bits:
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 			self._page = CSRStorage(page_bits, name=mem.name_override + "_page")
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 		else:
@@ -114,10 +107,10 @@ def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
114 107
 				]
115 108
 		
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 		if self._page is None:
117  
-			self.comb += port.adr.eq(self.bus.adr[word_bits:flen(port.adr)])
  110
+			self.comb += port.adr.eq(self.bus.adr[word_bits:word_bits+flen(port.adr)])
118 111
 		else:
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 			pv = self._page.storage
120  
-			self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:flen(port.adr)-flen(pv)], pv))
  113
+			self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:word_bits+flen(port.adr)-flen(pv)], pv))
121 114
 
122 115
 	def get_csrs(self):
123 116
 		if self._page is None:

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